Clever Geek Handbook

What is always @ * on the list of verilogues?

I'm a little confused as to what counts as an input when you use the @ * wildcard in the always blocking list. For example, in the following example, which signals are interpreted as inputs that cause re-analysis of an always block? From what I understand, clk and reset are not included as they do not appear on the right side of any procedural statement in an always block. a and b , because they both appear on the right side of procedural statements in an always block. But where I really got confused is ru and mux... Since they are used as test conditions in if and case reports, are they considered raw data? Is the block always revisited every time en and mux change ? I'm pretty much a noob and I haven't found a satisfying explanation in the 3 Verilog books. I've always found the explanations here very helpful. Thanks to

module example
( 
    input wire clk, reset, en, a, b,
    input wire [1:0] mux,
    output reg x,y, z
);

always @*    
begin  
 x = a & b;    
  if (en)
    y= a | b;
  case(mux)
    2'b00: z = 0;
    2'b01: z = 1;
    2'b10: z = 1;
    2'b11: z = 0;
  endcase
end
endmodule
+3


source to share


2 answers


Any signal that is read inside a block, and therefore could change the result of changing the block, if it changes the value will be included @*

. Any change in the read signal used should result in a re-evaluation of the block, as this could change the block outputs. As I'm sure you know, if you weren't using @*

, you would have specified these signals manually.

In the case of the code you provided it, there is any signal that:

  • Estimated on the right side of the job ( a

    and b

    )
  • It evaluated as part of the conditional ( en

    and mux

    )


... but this is any signal that will be evaluated for any reason. (I can't think of any other reasons right now, but maybe someone else can)

clk

and are reset

not included in the sensitivity list because they are not used. Just like that. There is nothing special about them; they are signals like any others.

+8


source


In your example, the following signals are included in the implicit sensitivity list:

a
b
en
mux


clk

and are reset

not included in the sensitivity list.

This is fully described in the IEEE Std for Verilog (e.g. 1800-2009). The IEEE specification is the best source for detailed information on Verilog. The documentation for your simulator can also describe how it works @*

.

+3


source






More articles:


All Articles