Verilog: Difference between `always` and` always @ * `

They are different! I used to think they are the same. But this is not the case.

always @ (*) means meaning something, the compiler will fill it in automatically. If it's combinational logic, use it! Therefore, you will not forget anything and the function will not fire.

always means that the offer will always be fulfilled! If there is no delay, the system has stopped and the result will not be obtained in the simulation! Very annoying.

For example, in the next logical part of the FSM state: if you use always instead of always @ (*), it doesn't work.

Below is a simple sequence detector I wrote where the two are different. You can write tb to run it if you like.

`timescale 1ns / 10ps

module seq_detect3 (// detects sequence 10110 in, // enter sequence clk, // hourly positive edge rst, // reset, synchronous active maximum match // out match, "1" to match);

input in, clk, rst;
output match;
wire in, clk, rst;
reg match;
reg [5:0] state, next_state;
parameter IDLE = 6'b000001;     //no bit matched
parameter STATE1 = 6'b000010;   //first 1 bit matched
parameter STATE2 = 6'b000100;   //first 2 bits matched
parameter STATE3 = 6'b001000;   //first 3 bits matched
parameter STATE4 = 6'b010000;   //first 4 bits matched
parameter STATE5 = 6'b100000;   //all 5 bits matched

//-----------S.M. & O.F.L.-----------
always @ (posedge clk) begin
    if(rst) begin
        state <= IDLE;
        match <= #1 0;
    end
    else begin
        state <= next_state;
        if(state == STATE5) begin
        match <= #1 1;
        end
        else begin
            match <= #1 0;
        end
    end
end 

//-----------next state logic-----------
always @(*) begin    //Can not replaced by always here!!
    case(state)
        IDLE:   if(in) next_state = STATE1; //0 keep, 1 next
                        else next_state = IDLE; 
        STATE1: if(in) next_state = STATE1; //0 next, 1 keep
                        else next_state = STATE2;
        STATE2: if(in) next_state = STATE3; //0 idle, 1 next
                        else next_state = IDLE;
        STATE3: if(in) next_state = STATE4; //0 s2, 1 next
                        else next_state = STATE2;   
        STATE4: if(in) next_state = STATE1; //0 next, 1 s1
                        else next_state = STATE5;
        STATE5: if(in) next_state = STATE3; //0 idle, 1 s3
                        else next_state = IDLE;
        default: next_state = IDLE;
    endcase
end

      

        
        
        
      

    

endmodule