Representing the addi command $ s1, $ 0, 4: write the value of control signals
I am doing my homework where I need to write down the value of control signals for 5 instructions and try to figure out a sample first (code below). The 5 instructions I need to do is
Address Code Basic Source
0x00400014 0x12120004 beq $16,$18,0x0004 15 beq $s0, $s2, exit
0x00400018 0x8e080000 lw $8,0x0000($16) 16 lw $t0, ($s0)
0x0040001c 0x02118020 add $16,$16,$17 17 add $s0, $s0, $s1
0x00400020 0xae08fffc sw $8,0xfffc($16) 18 sw $t0, -4($s0)
0x00400024 0x08100005 j 0x00400014 19 j loop
And the example he did is addi $ s1, $ 0.4. Right now I have this for this:
Address Code Basic Source
0x00400028 0x20110004 addi $16,$0,4 20 addi $s1, $0, 4
where I think the 4 in the base column are wrong. What is the correct answer?
Here's the example he made for this, and below is the diagram he means with control signals:
##--------------------------
# Example
# addi $s1, $0, 4
# Although not supported as in Figure 4.24, the instruction can be easily
# supported with minor changes in the control circuit.
instruction_address=0x00400028
instruction_encoding=0x20110004
OPcode=0b001000
Jump=0
Branch=0
Jump_address=0x00440010 # not used in this instruction
Branch_address=0x0040003C # not used in this instruction
Read_register_1=0b00000
Read_register_2=0b10001
Sign_extend_output=0x00000004
ALUSrc=1 # pick the value from sign_extend_output
ALUOp=0b00 # assume the same value as load/store instruction
ALU_control_input=0b0010 # add operation, as in load/store instruction
MemRead=0
MemWrite=0
MemtoReg=0 # select the ALU result
RegDst=0
Write_register=0b10001 #register number for $s1
RegWrite=1
##--------------------------
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Let's look at a breakdown of the first team: beq $s0, $s2, exit
.
Instruction address is the column address above: 0x00400014
. You also have the coding: 0x12120004
. An encoding is a machine instruction. Let's introduce the instructions in binary format 000100 10000 10010 0000000000000100
.
This is a type I instruction. The first group of six bits is the opcode, the second group of five is the source register, the third group of five is the temporary register, and the last group of sixteen is the immediate value.
Then the opcode 0b000100
. Since this is an I-type instruction, we don't jump to the target, so the signal Jump
is 0
. However, we are forking, so the signal Branch
is equal 1
.
To find Jump_Address
, even if it is ignored, check the least significant 26 bits: 10000 10010 0000000000000100
. Since the addresses are word-aligned, we can increase the range of reachable addresses by obtaining jump offsets as the difference between the next instruction and the target address. In other words, if my target address is equal to 8
bytes from the next command (relative addressing via PC), I will use it 2
to represent the offset. And so we have to shift the offset 2 bits to the left. So we get Jump_Address
= 10 00010 01000 0000000000010000
or 0x8480010
.
To find Branch_Address
, to be used, check the least significant 16 bits: 0000000000000100
. This character is expanded and shifted 2 bits to the left to get: 0000000000000000 0000000000010000
or 0x00000010
. It is the nearest value will be added to the program counter, which points to the next command 0x00400018
. So we end up with Branch_Address
= 0x00400028
. I am assuming that the label exit
points to the next instruction after the five you posted above, right after the instruction j
.
The registers are simple. Read_register_1
= 0b10000
and Read_register_2
= 0b10010
.
Sign_extend_output
- it's just the immediate extension of the field: 0x00000004
.
Incl. to the ALU control signals. ALUSrc
controls the multiplexer between the register file and the ALU. Since the instruction beq
requires the use of two registers, we need to select a register Read data 2
from the register file. We do not use a direct field to compute ALU, as with an instruction addi
. Consequently, ALUSrc
0
.
ALUOp
and ALU_control_input
are wired values that are generated from opcode. ALUOp
= 0b01
and ALU_control_input
= 0b0110
. Pg. 323 computer organization and design, 4th. Revised by Hennessey and Patterson and This page contains a table with the appropriate control signals for the instruction beq
. Pg. 318 has a table with ALU control bit mappings.
MemRead
and MemWrite
are 0
, since we do not access memory; MemToReg
X
(all the same), since it MemWrite
is 0; RegWrite
0
since we are not writing to the register file; RegDst
X
, since it RegWrite
is 0; and finally find Write_register
, take bits 16-20 (look at the multiplexer between the instruction memory and the register file), which 0b10010
.
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