Including Commands in the Makefile
I've read in Makefiles, but I still don't know how to start writing the following commands in the Makefile.
gcc -std=c89 A.c -c
gcc -std=c89 B.c -c
gcc -std=c89 C.c -c
gcc -std=c89 A.o B.o -o A
gcc -std=c89 C.o B.o -o C
A and C depend on B, but are separate programs.
This is what I ran into that doesn't work:
CC = gcc -std=c89
FILES = A.c B.c C.c
OUT = out
build: $(FILES)
$(CC) -o $(OUT) $(Files)
clean:
rm -f *.o core
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This is not a make-makefile, but that there must be a "tab" before gcc and rm, they are not spaces.
all: A C
A.o: A.c
gcc -std=c89 -c A.c
B.o: B.c
gcc -std=c89 -c B.c
C.o: C.c
gcc -std=c89 -c C.c
A: A.o B.o
gcc -std=c89 -o A A.o B.o
C: C.o B.o
gcc -std=c89 -o C C.o B.o
clean:
rm A C a.o b.o c.o core
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Try the following:
X1 = A
O1 = A.o B.o
X2 = B
O2 = C.o B.o
DBGFLAGS = -g -O0
CFLAGS = -W -Wall $(DBGFLAGS)
all: $(X1) $(X2)
$(X1): $(O1)
$(CC) $(LDFLAGS) -o $@ $(O1) $(LIBS)
$(X2): $(O2)
$(CC) $(LDFLAGS) -o $@ $(O2) $(LIBS)
.PHONY: clean
clean:
rm -f $(X1) $(O1) $(X2) $(O2) *~
Change 8 spaces per tab if copy doesn't.
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When you write a makefile, you usually start at the end and work your way back to the beginning. You start with the end product and give rules on how to do it from the starting point.
In this case, you seem to have two end products: A
and C
.
all: A C
If you don't specify a target on the command line, make will create the first target it sees in the makefile. Hence, you want this to be the first target in the file and the rest of the targets below. If you think of it as a tree, it is the root of the tree, and each item below is a branch of that tree.
It is also possible to define additional targets that are not included below this root. For example, many (most?) Makefiles include a named target clean
that removes any intermediate files that will be created during the build process. This will only be used if the user is calling make clean
, not as part of the issuance make
as a command.
In any case, then you talk about what each of them depends on, and how to create it from what it depends on:
A: A.o B.o
$(CC) -o A A.o B.o
C: B.o C.o
$(CC) -o B B.o C.o
Then (not here if needed) you tell how each file .o
depends on the file .c
. However, Gmake (almost ever, for example make
) has built-in rules to tell it how to compile a C or C ++ file to create a corresponding object file. It will be something like your makefile contains something like this at the top:
CC = gcc
.c.o:
$(CC) $(CFLAGS) -c $*.c
This passes the current CFLAGS value as flags to the compiler, so you want to set it to the flags you want - in your case:
CFLAGS = -std=c89
Usually you want to put this at the beginning of the makefile, usually before any of the targets.
I must add that this doesn't even come close to covering everything you could do in a makefile. There are many shortcuts which are very useful when you are dealing with a lot of files, but not very useful when you only have three source files.
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Assuming you are using GNU make , you can rely mainly on the built-in rules:
CFLAGS = -std=c89
LDFLAGS = -std=c89
A: A.o B.o
C: C.o B.o
This will execute the commands you listed. However, he doesn't care about cleaning or other things like thet. You don't have to, but the program has make
noticed when something needs to be recompiled / reloaded and done automatically.
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