Replacing Makefile line in dependency doesn't work

I have a folder structure where all my source files are in. / src / and all my object files are in. / obj / (with the same internal directory structure mirrored using path overrides). I created the following makefile:

$(EXECUTABLE): $(OBJECTS)
    @echo Linking $(EXECUTABLE)...
    $(CXX) $(LDLIBS) $(OBJECTS) -o $(EXECUTABLE)

%.o: $(subst o,cpp,$(subst obj/,src/,$@))
    @echo Building $@...
    $(CXX) $(CPPFLAGS) -c $(subst o,cpp,$(subst obj/,src/,$@)) -o $@

      

        
        
        
      

    

What does not work! Make sure the object files are up to date, even if the original file is actually older than the object file. On the other hand, if I do this:

obj/main.o: src/main.cpp
    @echo Building $@...
    $(CXX) $(CPPFLAGS) -c src/main.cpp -o $@

      

        
        
        
      

    

For every source file, it works great. I have checked and the two subst

give the same result (obj / main.o becomes src / main.cpp as expected). However, Make doesn't accept the dependency for some reason.

This gives me a lot of grief, can anyone explain where I am going wrong? I don't understand what's going on, I thought my replacement would work the same as it gives the same result. Am I not allowed to use subst

or $@

in dependencies or something?