How can I speed up my math operations in VHDL?

75 MHz is already pretty slow by FPGA standards today.

The problem is a modular operation that effectively involves division; and division is slow.

Think about what operations you need and if there is any way to refactor the calculation. If you sync pixels, it is not as if you had 32-bit integers; limited values ​​are easier to handle.

Another, if you need modulo 3 from an 8-bit (or 12-bit) number, you need to store all possible values ​​in a lookup table, which is fast enough.

Or sometimes you can multiply by 1/3 (X "5555") instead of dividing by 3, then multiply by 3 (which is one addition) and subtract to get the modulus. This pipeline is really good, but since X "5555" is only an approximation of 1/3, you need to check in simulation that it provides the correct output for each input. (for 16-bit inputs this is not a big simulation!) Modulo 9 expansion is easy.

EDIT:

Two points from your comments: Another possibility you have is to create an X2 clock (150 MHz) using Spartan clock generators, which gives you 2 cycles per pixel. Well pipelined code should be able to handle 150 MHz without too much trouble.

If not a conveyor!

PROCESS(Clk)
BEGIN
    if(rising_edge(Clk)) then
        for i in 0 to 2 loop
            case i is
                when 0 => temp1 <= a*data;
                when 1 => temp2 <= temp1*b;
                when 2 => result <= temp2*c;
                when others => null;
            end case;
        end loop;
    end if;
END PROCESS;

      

        
        
        
      

    

The first thing to understand is that the loop and case statements cancel each other out, so this makes it easy

PROCESS(Clk)
BEGIN
    if rising_edge(Clk) then
        temp1 <= a*data;
        temp2 <= temp1*b;
        result <= temp2*c;
    end if;
END PROCESS;

      

        
        
        
      

    

which is buggy! Testbench is also a bug, hides the problem.

Loop 1 presents data, a, b, c, and computes temp1 = Data * a.
In loop 2, temp1 is multiplied by the new value of b instead of the correct one!
Same thing again in loop 3!

Since testbench sets the inputs and leaves them constant, this won't catch the problem!

PROCESS(Clk)
BEGIN
    if rising_edge(Clk) then
        -- cycle 1
        temp1   <= a*data;
        b_copy  <= b;
        c_copy1 <= c;
        -- cycle 2
        temp2   <= temp1*b_copy;
        c_copy2 <= c_copy1;
        -- cycle 3
        result  <= temp2*c_copy2;
    end if;
END PROCESS;

      

        
        
        
      

    

I like to comment on each cycle; every term I use in a loop must come from the immediately preceding loop, either by calculation or from a copy.

At least it works, but it can be reduced to 2 clock cycles and less copy registers because in this example the four inputs are independent (and I assume no action is required to prevent overflow). So:

PROCESS(Clk)
BEGIN
    if rising_edge(Clk) then
        -- cycle 1
        temp1   <= a * data;
        temp2   <= b * c;
        -- cycle 2
        result  <= temp1 * temp2;
    end if;
END PROCESS;