Getting micro-ops for CALL
I am trying to understand how the fetch cycle will be written in micro-ops for a 32 bit CALL instruction to be fetched by the processor.
MAR is 16 bits wide
MDR is 8 bits wide
PC is 16 bits wide
IR is 16 bits wide
Temp registers are 16 bits wide
My question has to do with the fact that an instruction is 32 bits, the 16-bit characters represent the opcode, and the lower 16 bits represent the destination address we are navigating to.
The sampling cycle is as follows:
MAR <- PC
MDR <- M(MAR)
IR <- MDR opcode
MAR <- MDR address
PC <- PC + 1
Since MDR is only 8 bits wide, how can we tune this fetch loop to account for all opcode and address, each 16 bits wide?
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I am assuming a small endian architecture for working with memory. Also I am assuming that one of the registers is called SP and is the stack pointer growing down. Access to the high part and the low part of the PC, TEMP and IR is done independently.
/* FETCH................ */
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;low 8 bits of opcode
IRlow <- MDR
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;high 8 bits of opcode
IRhigh <- MDR
/* DECODE AND EXECUTE................ */
if MDR is opcode for CALL...
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;low 8 bits of destination
TEMPlow <- MDR
MAR <- PC
PC <- PC+1
MDR <- M(MAR) ;high 8 bits of destination
TEMPhigh <- MDR
SP <- SP-1
MAR <- SP
MDR <- PChigh
M(MAR) <- MDR ;store hi part of next instruction in stack
SP <- SP-1
MAR <- SP
MDR <- PClow
M(MAR) <- MDR ;store low part of next instruction in stack
PC <- TEMP ;update PC to jump to the called address
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