How can I achieve something like RLOC Xilinx in FPGA Altera?
So, to answer my own question, after some consultation with some of the Altera guides and some trial and error, I found that this pretty much does what I want.
module synchronizer (input wire dat_i,
input wire out_clk,
output wire dat_o);
(* altera_attribute = "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2; -name SYNCHRONIZER_IDENTIFICATION \"FORCED IF ASYNCHRONOUS\"" *)
logic [1:0] out_sync_reg;
always_ff@(posedge out_clk) begin
out_sync_reg <= {out_sync_reg[0],dat_i};
end
assign dat_o = out_sync_reg[1];
endmodule
I tested this by setting a global sync detection and noticed that TimeQuest found and parsed the correct metastability paths.
This works well even when dat_i
committed clk_a
and out_clk
managed clk_b
and where two hours are set as:
set_clock_groups -asynchronous -group {clk_a}
set_clock_groups -asynchronous -group {clk_b}
This way, false paths are created between all connections from the registers at clock speeds clk_a
for registers synchronized withclk_b
set_max/min_delay
doesn't work as it is ignored (as pointed out by Altera) if the two ticks are in different asynchronous clock groups.
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Altera does not support style constraints RLOC
. It seems to have something to do with the underlying physical architecture. I believe they provide ALM redundantly and combine columns during the chip test to improve yield, so relative location constraints will not translate as expected to a physical device.
If you are concerned about timing chain placement, you can enable timing chain detection using SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
and SYNCHRONIZER_IDENTIFICATION
the QSF settings (see also this answer ).
If you just want to provide a specific time value, use a time limit set_max_delay
and set_min_delay
be on your way.
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