Components Not Generated Properly in VHDL Generate

I am working on a VHDL project to design an 8 bit ALU using a previously developed one bit ALU. To do this, I use the generate statement to generate bits 1-6 from the ALU, and bits 0 and 7 are processed outside of this block. What happens when I go to simulate an ALU is that bit 1-6 never change value, no matter what the inputs are. I know that one bit ALU works fine because an instance of 8 one-bit ALUs manually works as expected.

I think what is happening for some reason, the component instance inside the generate block is not compiling as expected. When I go to run a simulation in ModelSim, messages appear in the transcript that "component instance bit1_6: bitleese is not linked." In an attempt to illustrate what's going on, the code I posted for the firstGen architecture doesn't compile, saying "No statement with label bit1_6: bitslice was found" (using FOR ALL: ... masks bad behavior since lsb and msb are accurate). Does anyone know what's going on?

ENTITY alu8bit IS
PORT( A, B : IN bit_vector(7 downto 0);
    P,K,R : IN bit_vector(3 downto 0);
    ci : IN bit;
    Z : OUT bit_vector(7 downto 0);
    co : OUT bit);
END;

ARCHITECTURE firstGen of alu8bit IS

COMPONENT bitslice 
    PORT(a, b, ci: IN bit;
        P, K, R : IN bit_vector(3 downto 0);
        ri, cn: OUT bit);
END COMPONENT;

FOR bit1_6: bitslice USE ENTITY work.one_bit_alu(alu_1_bit);
FOR others : bitslice USE ENTITY work.one_bit_alu(alu_1_bit);
signal c : bit_vector(7 downto 1);
BEGIN
    lsb : bitslice PORT MAP(A(0), B(0), ci, P, K, R, Z(0), c(1));
    GEN_MIDDLE_BITS: FOR I IN 1 TO 6 GENERATE
        bit1_6 : bitslice PORT MAP(A(I), B(I), c(I), P, K, R, Z(I), c(I+1));
    end generate;
    msb : bitslice PORT MAP(A(7), B(7), c(7), P, K, R, Z(7), co);
END;

      

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The generate statement adds an extra layer of hierarchy to the namespace. When using an internal configuration specification, you are limited to customizing the components in the immediate scope. Anything inside the generated (or block) becomes unavailable. You can use the declarative scope of the generate statement to specify the configuration binding for intermediate slices:

GEN_MIDDLE_BITS: FOR I IN 1 TO 6 GENERATE
  for bit1_6 : bitslice use entity work.one_bit_alu(alu_1_bit);
begin
    bit1_6 : bitslice PORT MAP(A(I), B(I), c(I), P, K, R, Z(I), c(I+1));
end generate;

      



You might also consider using an external config declaration to keep everything together. If desired, configurations can be created in the same way as an instance of the direct VHDL-93 object.

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