Included parent Makefile directory

I want to describe the dependencies between swaps in a file that can include the top level Makefile

. This allows for recursive tuning (with all the power of instantiation variables and relative trajectory), but with all the dependencies described at the top level to increase compilation speed and parallelism.

For example, suppose we have a directory tree that looks like this:

project/
|-- lib1
|   |-- Makefile
|   `-- Makefile.reg
|-- lib2
|   |-- Makefile
|   `-- Makefile.reg
|-- Makefile
`-- Makefile.reg

      

The file for the file project/lib1/Makefile.reg

might look like this:

REG := lib1
include ../Makefile.reg

      

The file for the file project/lib2/Makefile.reg

might look like this:

REG := lib2
DEP := lib1
include ../Makefile.reg

      

The file project/Makefile.reg

will look like this:

$(REG)_DIR = ????
$(REG): $(DEP)
  $(MAKE) -C $($@_DIR)

      

Finally, the top level project/Makefile

looks like this:

include $(shell find . -name "Makefile.reg")

      

The top level now Makefile

has all the dependency information for each target and can intelligently invoke recursive make and use full parallelism while keeping the dependency tree intact.

The problem is I am not sure how to communicate to project/Makefile.reg

know what the current swap path is Makefile.reg

. make

will always be called from the top level directory, so $(shell pwd)

it will always report project/

. One solution would be to include a line from this SO answer, however I would like each to Makefile.reg

only specify the target and optional list of dependencies.

Is there a way to enable directory path detection in the shared one project/Makefile.reg

instead of putting a newline in each sub-layout Makefile.reg

? In other words, is it possible to include the makefile in the parent makefile? I see potential in some different analysis of the variable MAKEFILE_LIST

.

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As the documentation snippet included in the response to your associated ticket shows. The value is MAKEFILE_LIST

updated as it is released. The last entry in the list is the current makefile, which makes the penultimate entry in the list the last included makefile. If you want to argue that the main one project/Makefile.reg

will only be included from the subdirectory makefile, then he can just examine that entry in MAKEFILE_LIST

.

Alternatively, you can simply define the canned recipe in the master Makefile

and invoke it in each makefile to determine the appropriate targets.

Unfortunately, it makes the penultimate entry a little more difficult than pleasant. But the following should work:



FOO=a b c d e f g
BAR=h i j k l m n
BAZ=o p q r s t u
QUX=v w x y z 1 2

penultimateword = $(wordlist $(words $1),$(words $1), x $1)

REG=FOO
$(REG)_DIR= $(call penultimateword,$($(REG)))
$(info REG_DIR=$($(REG)_DIR))

REG=BAR
$(REG)_DIR= $(call penultimateword,$($(REG)))
$(info REG_DIR=$($(REG)_DIR))

REG=BAZ
$(REG)_DIR= $(call penultimateword,$($(REG)))
$(info REG_DIR=$($(REG)_DIR))

REG=QUX
$(REG)_DIR= $(call penultimateword,$($(REG)))
$(info REG_DIR=$($(REG)_DIR))

all: ;

      

The inspiration for the above comes from a function chop

from the fantastic GMSL .

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