Should Chisel generate testlench verilog logic?
I have the following test code and call chiseMain with --genHarness. Verilog is created for the wire harness, but it doesn't have any logic from the Tester class. Any thoughts on why I am not getting the logic I expect? I am using Chisel 2.10.
Code:
class TestMultiPortedMem(c: MultiPortedMem) extends Tester(c) {
var i = 0
// Write address as data
for (p <- c.io.wports) {
poke(p.wen, 1)
poke(p.addr, i)
poke(p.wdata, i)
step(1)
i = i + 1
}
// Read it back
i = 0
for (p <- c.io.rports) {
poke(p.addr, i)
step(1)
expect(p.rdata, i)
i = i + 1
}
}
object TestMem {
def main(args: Array[String]): Unit = {
//chiselMainTest(Array[String]("--backend", "v", "--genHarness"),
chiselMainTest(args,
() => Module(new MultiPortedMem(1,1,1,128,32))){c => new TestMultiPortedMem(c)}
}
}
Generated by Verilog:
module test;
reg [0:0] io_enable;
reg [6:0] io_rports_0_addr;
reg [31:0] io_wports_0_wdata;
reg [6:0] io_wports_0_addr;
reg [0:0] io_wports_0_wen;
reg [6:0] io_rwports_0_addr;
reg [31:0] io_rwports_0_wdata;
reg [0:0] io_rwports_0_wen;
wire [31:0] io_rports_0_rdata;
wire [31:0] io_rwports_0_rdata;
reg clk = 0;
parameter clk_length = `CLOCK_PERIOD;
always #clk_length clk = ~clk;
/*** DUT instantiation ***/
MultiPortedMem
MultiPortedMem(
.clk(clk),
.io_enable(io_enable),
.io_rports_0_addr(io_rports_0_addr),
.io_wports_0_wdata(io_wports_0_wdata),
.io_wports_0_addr(io_wports_0_addr),
.io_wports_0_wen(io_wports_0_wen),
.io_rwports_0_addr(io_rwports_0_addr),
.io_rwports_0_wdata(io_rwports_0_wdata),
.io_rwports_0_wen(io_rwports_0_wen),
.io_rports_0_rdata(io_rports_0_rdata),
.io_rwports_0_rdata(io_rwports_0_rdata)
);
/*** resets && VCD / VPD dumps ***/
initial begin
end
task check_value;
input [255:0] data;
input [255:0] expected;
begin
if (data == expected)
$display("PASS");
else
$display("FAIL");
end
endtask
always @(posedge clk) begin
$display("MultiPortedMem.io_rwports_0_rdata: 0x%x, MultiPortedMem.io_rports_0_rdata: 0x%x, ", io_rports_0_rdata, io_rwports_0_rdata);
end
endmodule
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The 2.10 drill bit is too large to support the option --genHarness
. Since this is a feature still in development, there is no invalid flag warning. You want to use Chisel 2.18 to get the correct behavior from --genHarness
.
A new release on Sonatype is coming soon, leading to numbered releases to the current state of the head of the master Git master.
In general, however, the parameter --genHarness
does not support generator logic, which acts as a tester. Instead, it generates a Verilog test bench that uses encoded command line inputs that allow simulation values for top-level I / O and state elements to be changed.
This generated tester is run in the VCS process generated by the bit tester, which then sends commands peek
, poke
and step
to the VCS via IPC. Since the testbench created with --genHarness
is designed to accept these inputs, the Verilog instance of the object under test can be tested in the same way as it would when simulating C ++.
While it is theoretically possible to have a framework for creating standalone Verilog testers encoding some logic in an Tester
-extension class , this would require embedding the behavior of a Scala program in Verilog simulations, which is a significantly more rigid solution than the existing use of IPC for --genHarness
.
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