Using the same make file in a separate directory
I have a makefile in a directory foo
and I would like to use the same makefile in a subdirectory bar
. I did the following:
all:
<do work in foo>
cd bar;
make -f ../Makefile <target to make in bar>
It gets very messy when I try to target variable values as I need to pass them on the command line when called make
in bar
. Is there a cleaner way to do this?
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I can't tell from the question if the following solution is right for your needs, it may or may not work.
If your situation is that you just want to use the same functionality Makefile
, there include
might be a solution. You can create Makefile
in the directory bar
where you do whatever you need to do for bar
, and in addition you do:
include ../foo/Makefile
Warning! It doesn't work directly. There cannot be two recipes with the same name. For example, if you want to foo/Makefile
run recipeBar
for all
, and you want to foo/Makefile
perform recipeFoo
, and recipeBar
to all
, the following does not work. :
Foo / Makefile:
.PHONY: all
all:
recipeFoo
bar / Makefile:
.PHONY: all
all:
reciveBar
include foo/Makefile
Instead, recipes must be separated into unique names. However, dependency rules can be multiple times, so this is not really a problem to solve this problem. So the following will work:
Foo / Makefile:
.PHONY: all
all: allFoo
.PHONY: allFoo
allFoo:
recipeFoo
bar / Makefile:
.PHONY: all
all: allBar
.PHONY: allBar
allBar:
recipeBar
include foo/Makefile
Now if you run make
in bar
, it will run recipeFoo
and recipeBar
. If the sequence is important to you, but recipeFoo
should run before recipeBar
, enter allBar
depending on allFoo
, for example:
bar / Makefile:
.PHONY: all
all: allBar
.PHONY: allBar
allBar: allFoo
recipeBar
include foo/Makefile
If you want your target variables to be available when you call another make
(for which I recommend using $(MAKE)
not make
), you can export your variables - with the appropriate consequences (risk of environment space overflow in some versions of Windows.
For example, if you have a target variable FOO
for target all
in Makefile
, and you want Submake.mak
that variable to be known when called , it works like this:
Makefile:
all: export FOO:=bar
.PHONY: all
all:
$(MAKE) -f Submake.mak
Submake.mak:
.PHONY: all
all:
echo $(FOO)
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