How to write a verilog test bench to loop through 4 inputs?
I need to create verilog and testbench code for this circuit.
I have a design for this here.
module prob1(input wire a,b,c,d, output wire out);
assign out = (a||d)&&(!d&&b&&c);
endmodule
Here's what I have in the test bank so far.
module prob1_tb();
reg a,b,c,d;
wire out;
prob1 prob1_test(a,b,c,d, out);
initial begin
for(i=0; i=16; i=i+1)
<loop code here>
end
end
endmodule
Now I guess I have a problem with how I can convert this number to those 4 inputs used in the circuit. Or is there a better way to do this?
Here's a simple way to use the concatenation operator:
module prob1(input wire a,b,c,d, output wire out);
assign out = (a||d)&&(!d&&b&&c);
endmodule
module prob1_tb();
reg a,b,c,d;
wire out;
prob1 prob1_test(a,b,c,d, out);
initial begin
$monitor(a,b,c,d,out);
for (int i=0; i<16; i=i+1) begin
{a,b,c,d} = i;
#1;
end
end
endmodule
/*
Output:
00000
00010
00100
00110
01000
01010
01100
01110
10000
10010
10100
10110
11000
11010
11101
11110
*/
Yes, there are better ways to test your logic. The first thing to do is enter random values (see Functions $urandom
in IEEE Std 1800-2009). Of course, you also need to perform checks on your inference using a model, which is trivial in your case.
Depending on how much time (and training) you have, you can accept a standard stream like the Universal Validation Methodology (UVM). People build their careers around verification.
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