Makefile without specifying source file
I have a makefile like this:
# Makefile for VocabLearn
MACHTYPE=$(shell uname -m)
GCC = g++
CC=gcc
# OPTFLAGS=-g2
OPTFLAGS=-O3 -ffast-math -Wall -mfpmath=sse -msse2 -funroll-loops -march=core2
OTHERFLAGS=-Wall -fopenmp
INCLUDE_PATH=-I../lib/ann_1.1/include/ANN -I../lib/ann_1.1_char/include/ANN \
-I../lib/imagelib -I../VocabLib -I../lib/zlib/include
LIB_PATH=-L../lib -L../VocabLib -L../lib/zlib/lib
OBJS=VocabLearn.o
LIBS=-lvocab -lANN -lANN_char -limage -lz
CPPFLAGS=$(INCLUDE_PATH) $(LIB_PATH) $(OTHERFLAGS) $(OPTFLAGS)
BIN=VocabLearn
all: $(BIN)
$(BIN): $(OBJS)
g++ -o $(CPPFLAGS) -o $(BIN) $(OBJS) $(LIBS)
clean:
rm -f *.o *~ $(LIB)
When I "create" it at the prompt, it works fine and outputs the following information: (I am using Mac OS, C ++ means clang compiler)
C ++ -I ../ lib / ann_1.1 / include / ANN -I ../ lib / ann_1.1_char / include / ANN -I ../ lib / imagelib -I ../ VocabLib -I ../ lib / zlib / include -L ../ lib -L ../ VocabLib -L ../ lib / zlib / lib -Wall -fopenmp -O3 -ffast-math -Wall -mfpmath = sse -msse2 -funroll-loops - march = core2 -c -o VocabLearn.o VocabLearn.cpp
g ++ -o -I ../ lib / ann_1.1 / include / ANN -I ../ lib / ann_1.1_char / include / ANN -I ../ lib / imagelib -I ../ VocabLib -I ../ lib / zlib / include -L ../ lib -L ../ VocabLib -L ../ lib / zlib / lib -Wall -fopenmp -O3 -ffast-math -Wall -mfpmath = sse -msse2 -funroll-loops - march = core2 -o VocabLearn VocabLearn.o -lvocab -lANN -lANN_char -limage -lz
I just want to know how this makefile works. As you can see, since this makefile does not specify which source code should be compiled, how does the compiler know that it is "VocabLearn.cpp" that it should process? (My guess is that it will search for the original file according to the object file name, VocabLearn.o). This line seems a little strange to me:
g++ -o $(CPPFLAGS) -o $(BIN) $(OBJS) $(LIBS)
Why is there "-o" before "$ (CPPFLAGS)"?
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This makefile uses implicit rules to compile source files. Rule:
$(BIN): $(OBJS)
requests object files in OBJS
and already knows how to build VocabLearn.o
if there is a file VocabLean.cpp
.
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Basically there is an implicit rule for converting * .cpp files to * .o files, however you must have * .o as a dependency in one of your targets. In this Makefile, you have VocabLearn.o as a dependency for $ (BIN). This way VocabLearn.o is automatically generated from the VocabLearn.cpp file.
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