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What does single multiplication and hardware division mean?

I am going through the datasheet and reading "Single multiplication and hardware division" as part of the STM32 specs, I'm not sure I understand what that means. From what I've read on the web, multiplication is usually easier to calculate than division. Does this mean that STM can compute both multiplication and division in one cycle?

Please, help.

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When it comes to the multiplier, this means that it only takes one clock cycle to complete the operation (that's for 100 MHz, 10 nanoseconds).

However, the split is usually done iteratively, bit by bit, and the specific implementation (set of core commands) should be studied.

Looking at the Cortex M-Series , you can see that the multiplication is actually one-time, however the division takes 2-12 cycles, and in a footnote regarding this:



Subdivision operations use early completion to minimize the number of cycles required based on the number of leading and zeros in the input operands.

Added:

Note, however, that the only INTxINT multiplications are single-cycle, whereas LONGxLONG last 3-5 cycles (as LONGxLONG mult can be done as a combination of INTxINT multiplications and complements)

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