How to customize makefile options
I have a Makefile that creates a 32-bit and 64-bit version of a project:
#############################
# 32 bit variant of test tool
#############################
hidtest_32: $(OBJS_32)
$(CXX_32) -m32 -g $^ $(LIBS) -o hidtest_32
hid_32.o: hid.c
$(CC_32) -m32 $(CFLAGS) $< -o hid_32.o
../hidtest/hidtest_32.o: ../hidtest/hidtest.cpp
$(CC_32) -m32 $(CFLAGS) $< -o ../hidtest/hidtest_32.o
#############################
# 64 bit variant of test tool
#############################
hidtest_64: $(OBJS_64)
$(CXX_64) -m64 -g $^ $(LIBS) -o hidtest_64
hid_64.o: hid.c
$(CC_64) -m64 $(CFLAGS) $< -o hid_64.o
../hidtest/hidtest_64.o: ../hidtest/hidtest.cpp
$(CC_64) -m64 $(CFLAGS) $< -o ../hidtest/hidtest_64.o
As you can see, both options use the same build procedure, except that the number has 32
been replaced with 64
.
I have tried something like
hidtest64: ARCH=64
hidtest64: hidtest_64
hidtest32: ARCH=32
hidtest32: hidtest_32
hidtest_%: $(OBJS_$(ARCH))
$(CXX_$(ARCH)) -m$(ARCH) -g $^ $(LIBS) -o $@
which doesn't work as expected. I guess I will need to access the portion of the target that matches %
, which I was unable to do.
Is there a way to combine the two options into one (parameterized) one?
source to share
If you are using GNU Make you can write a function (callable macro). Single $
is replaced at runtime $(call ...)
double $
is replaced at runtime $(eval $(call ...))
. Background information is here .
define add_target
$(info compiling hidtest_$(1)) # logged when doing $(call ...)
$$(info evaluating hidtest_$(1)) # logged when doing $(eval $(call ...))
hidtest_$(1): $(OBJS_$(1))
$(CXX_$(1)) -m$(1) -g $$^ $(LIBS_$(1)) -o $$@
endef
$(eval $(call add_target,32))
$(eval $(call add_target,64))
source to share