Reading invalid data while indexing a nested array
I am using dcache on a pipelined processor. My dcache is 2 way associativity with 2 words per block and 8 indices This is how I initialized the cache structure.
typedef struct packed {
logic [25:0] tag;
logic valid, dirty;
word_t [1:0] data;
} block_t;
typedef struct packed {
block_t [1:0] way;
} dcache_t;
dcache_t [7:0] cache;
So, to access the word: cache [i] .way [j] .data [k]
I can write to the cache fine.
index
, way
and sel
are variables that use combination logic to determine where to index.
So, for example, this line is in my register always_ff
for cache.
cache[index].way[way].data[sel] = ccif.dload[CPUID];
Following the above lines of code following the data stored in the cache: for index = 6
, way = 0
,sel = 0
cache[6].way[0].data[0] <== 0x01234567
and after the next clock cycle index = 6
, way = 0
,sel = 1
cache[6].way[0].data[1] <== 0x89ABCDEF
Since I am downloading two words at a time.
... but when I read it, using index = 6
, way = 0
,sel = 1
dcif.dmemload = cache[index].way[way].data[sel];
The following is read from my cache
dcif.dmemload <== 0xCDEF0123
I am getting the wrong value and don't know why, as the value in the cache remains the same and hasn't changed.
This is the current state of my cache partition while reading
+-------+------------+------------+
| index | data[1] | data[0] |
+-------+------------+------------+
| 6 | 89ABCDEF | 01234567 |
+-------+------------+------------+
Any ideas? I'm confused because my indexing works fine when writing, but something strange happens when reading
Edit: reading the value doesn't always offset 2 bytes. I'm not sure if I have too many nested arrays.
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This is a bug in ModelSim / Questa and is fixed in the next version.
The solution is to not make the entire nested array all packed . You probably didn't want your cache to be packed anyway. You shouldn't be packing your arrays unless you need access to the whole array as a single integer value.
dcache_t cache[7:0];
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