<= Verilog assignment operator
"<=" is called non-blocking assignment in Verilog, which makes a bigger difference than "=" is called blocking assignment due to event scheduling in any vendor-based simulators.
It is recommended to use a non-blocking assignment for sequential logic and a blocking assignment for combinational logic, only then it detects the correct hardware logic during synthesis.
Non-blocking statements in a sequential block will trigger a flip flop in real hardware.
Always remember not to mix blocking and non-blocking in any sequential or combinational block.
During the planning process of the simulator:
There are four areas and the order of command execution as follows
1) Active region --Blocking assignments --Evaluation of RHS of non-blocking assignments(NBA) --Continuous assignment --$display command --Evaluate input and output of primitives 2) Inactive region --#0 blocking assignments 3) NBA(non-blocking assignment update) --update LHS of non-blocking assignments (NBA) 4) Postponed --$monitor command --$strobe command
Using a blocking "=" assignment for two variables in the same time slot causes a race condition
eg: Verilog code with race condition,
always @(posedge Clock) BCD0 = 0; // Usage of blocking statements should be avoided always @(posedge Clock) BCD1 = BCD0;
To avoid race conditions, use the non-blocking "<=" operator
eg:
always @(posedge Clock) BCD0 <= 0; // Recommended to use NBA always @(posedge Clock) BCD1 <= BCD0;
When this block is executed, two events are added to the non-blocking assignment update queue. Hence, it updates BCD1 from BCD0 at the end of the time step.
Using a non-blocking assignment "<=" in a continuous assignment operator is not allowed according to the Verilog LRM and will result in a compilation error.
eg:
assign BCD0 <= BCD1; //Results in compilation error
Use only NBA in procedural assignment instructions,
- initial and - always blocks
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This is called a "non-blocking" assignment. The non-blocking assignment allows designers to describe updating the state of the machine without having to declare and use temporary storage variables.
For example, in this code, when you use a non-blocking assignment, its action will not be registered until the next clock cycle. This means that the order of the assignments does not matter and will give the same result.
Another assignment operator, '=', is called lock assignment. When "=" assignment is used, for logic purposes the target variable is immediately updated.
Understand this more deeply, please take a look at this example (from Wikipedia):
module toplevel(clock,reset); input clock; input reset; reg flop1; reg flop2; always @ (posedge reset or posedge clock) if (reset) begin flop1 <= 0; flop2 <= 1; end else begin flop1 <= flop2; flop2 <= flop1; end endmodule
In this example, flop1 <= flop2
and flop2 <= flop1
will replace the values of these two reg
s. But if we used the lock assignment =
, this would not happen and the behavior would be wrong.
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"<=" is the non-blocking assignment operator in verilog. "=" is the lock assignment operator.
Consider the following code.
[email protected](clk) begin a=b; end [email protected](clk) begin b=a; end
The values of a and b are always exchanged using two different blocks. Using "=" here caused a race condition. i.e. the variables a and b are changed simultaneously. Using "<=" will avoid the race.
alwa[email protected](clk) begin a<=b; end [email protected](clk) begin b<=a; end
Hope I helped too.
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Since people have already explained the blocking / non-blocking situation, I'll just add this here to help with understanding. "<=" replaces the word "gets" when you read the code
For example:
.... // Verilog code here
A <= B // reads it as A gets B
When does A get B? In a given time slot, think about everything that happens in the hardware in the time slots, for example, in a particular sampled event driven by a clock. If the "<=" operator is used in a clock module that runs every 5 ns, imagine that A receives B at the end of this time interval, after all other "blocking" assignments are enabled and at the same time blocking assignments.
I know it's confusing, it gets better when you use and mess up a bunch of projects and learn how it works.
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<=
is a non-blocking destination. Operators <=
are executed in parallel. Think about a pipelined architecture where we come across the use of such assignments.
A small example:
// initialize a, b, c with 1, 2 and 3 respectively.
initial begin
a <= 1
b <= 2
c <= 3
end
[email protected](clock.posedge)
begin
a <= b
b <= c
c <= a
end
After the first hours:
a = 2, b = 3, c = 1
After the second time zone:
a = 3, b = 1, c = 2
After three second hours:
a = 1, b = 2, c = 3
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** Your question was rejected because this is something you can easily find in a basic verlog or book. Not very helpful for you or others to be asked in a forum like this.
As said, this is a "Non Blocking <=" assignment widely used for sequential logical design because it can best mimic it. This is why . Basically, a delayed (poser clock here) is something like a RHS scheduling schedule for the LHS after a specified delay and moving to the next statement (emulating a serial) in the stream, as opposed to "Blocking =", which actually delays execution of the next statement in according to the specified delay (emulation of combinational)
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