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Synthesis of VHDL if statements without elsif and else conditions

I'm trying to get a better understanding of how synthesis works for a process like this where no other conditions are specified.

I assume this is not the way to code it because I am not considering other options, but my question is, how is this interpreter interpreted?

process(clock)
begin
if (clock'event and clock ='1') then 
  if sel0 = '1' then qout <= A - B;    end if; 
  if sel1 = '1' then qout <=  qout sra 2;        end if;
end if;
end process;
Operators

IF will be synthesized into multiplexers. I think for this example both muxes will be chained together with the D register at the end for the registered out value. I am assuming the value of qout when sel0 is '0' and sel1 is '0'? What happens to each multiplexer when its selector is "0"? Does the network keep the same result by pulling out the latch?

Thank.

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3 answers


To show and learn how synthesis tools implement a design, you can, for example, synthesize with the Altera Quartus II and then use the built-in RTL viewer to show a high-level view of the resulting design.

The code using 1 bit vectors to simplify the structure gives the result shown below.

enter image description here

So this shows a trigger that is updated every loop with a value:

  • qout_sra_2

    if sel1 = '1'

  • a_minus_b

    if sel1 = '0'

    usel0 = '1'

  • qout

    (reassign with the same value) if sel1 = '0'

    andsel0 = '0'

Thus, it is equivalent with:

if clock'event and clock ='1' then 
  if sel1 = '1' then
    qout <= qout sra 2;
  elsif sel0 = '1' then
    qout <= A - B;
  else
    qout <= qout;
  end if; 
end if;


Other synthesis tools can implement it in another, for example in Xilinx ISE, which uses clock synchronization on the trigger, thus giving the result below.

enter image description here

So this shows a trigger that is updated if sel0

either sel1

'1'

with a value:

  • qout_sra_2

    if sel1 = '1'

  • a_minus_b

    , if a sel1 = '0'

Thus, it is equivalent with:

if clock'event and clock ='1' then 
  if not ((sel0 = '0') and (sel1 = '0')) then  -- (sel0 = '1') or (sel1 = '1')
    if sel1 = '1' then
      qout <= qout sra 2;
    else
      qout <= A - B;
    end if;
  end if;
end if;
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Basically you get a multiplexer and a register (in addition to the logic that handles the computation for each input, of course). There is no need for a latch, because the register will be clocked, so the input network can be purely combinational.

There is also no need for two multiplexes. Because of how signal assignment works in VHDL, the following code segment:

if sel0 = '1' then
  qout <= A - B;
end if; 
if sel1 = '1' then
  qout <= qout sra 2;
end if;


equivalent to:

if sel1 = '1' then
  qout <= qout sra 2;
elsif sel0 = '1' then
  qout <= A - B;
end if;

A later assignment overrides the previous assignment if both conditions if

are true. It is understood that after this "do nothing", ie. "Otherwise the clock does not allow register." The logic can be boiled down to a multiplexer that only depends on sel1

(if sel1

- '0'

, the network pin is what would be chosen sel0

, or not required since it will not be synchronized). The clock resolution for the register will be sel0 or sel1

. This is how I would do it, at least.

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If no operator if

executes, it qout

retains its current value. This will initially be the leftmost element in a declaration like '0' for bit

and 'U' for std_ulogic

. Synths may complain about no valid initialization or the default "0" or "1".

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