SystemVerilog: How to wire a C function using a DPI call in a VCS simulator?

I have the following files:

C file with functions:

//funcs.c

#include <stdio.h>

void something() {
    printf("something\n");
    sayHello();
}

      

System Verilog File:

//hello_world.v

module kuku;
    export "DPI-C" function sayHello;
    import "DPI-C" function void something();
    initial something();
    function int sayHello ();
        $display("hello world");
        sayHello = 1;
    endfunction
endmodule

      

How can I compile it and make it work like that when I call something()

from SV it will call the C function and when I call sayHello()

from C it will call the SV function?

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4 answers


Answering myself:

When SV code is compiled using VCS, it is translated to C code first.

A exporting

function from SV generates a C header file vc_hdrs.h

which must be included in the C file.

Thus, the change I made in the C file was to add the line:

#include "vc_hdrs.h"

      

Then I just added the C functions file to the VCS compile command:



> vcs -sverilog hello_world.v funcs.c

      

It works!

I am getting output:

something
hello world

      

,

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A solution that works with all simulators that follow IEEE Std 1800-2012 should have #include "svdpi.h"

a keyword prefix extern

in front of all methods exported to C. funcs.c should look like this:

#include <stdio.h>
#include "svdpi.h"

extern int sayHello();

void something() {
    printf("something\n");
    sayHello();
}

      



Examples from IEEE Std 1800-2012

  • & section; H.10.2 Example 2 - Simple packed matrix application
  • & section; H.10.3 Example 3 - Application with complex combination of types
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I see that you named the SystemVerilog file as a .v extension. Not sure if this works or not. But let's say if its hello_world.sv

Your command line should look like this (for Questa Simulator),

qverilog hello_world.sv funcs.c

      

"qverilog" is to compile and run SystemVerilog files.

It's all. There is no need to add additional header files.

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Hi I provided a good example in this post fooobar.com/questions/162135 / ...

Synopsys VCS

1) You will compile the C code using flags and enter the definitions you want to add. In our case, our C code needs to define PYTHON_PATH

#GCC in two steps for shared object
gcc -g -D 'PYTHON_PATH="'$PYTHON_DIR'"'  -fPIC -Wall -I${VCS_HOME}/include -I/usr/include/python2.6/ -lpython2.6 -c ${PROJECTDIR}/verification/PVE/keycontrol/tb/keycontrol_C_code_wrapper.c 
gcc -fPIC -shared -o keycontrol_C_code_wrapper.so  keycontrol_C_code_wrapper.o 

      

2) You are developing VCS by linking python librar with -LDFLAGS '-lpython2.6'

vcs -timescale=1ps/1ps -ntb_opts uvm -lca -kdb -full64 keycontrol_tb_top -debug_access+all+reverse  -LDFLAGS '-lpython2.6'

      

3) You run the generated simulation file. You call simv including -sv_lib keycontrol_C_code_wrapper to import the shared C object.

#RUN C CODE
./simv -gui -ucli +DVE +UVM_NO_RELNOTES  -l simv.log  +UVM_TESTNAME=keycontrol_basic_test -do ../../verification/PVE/keycontrol/tools/keycontrol_ucli_init.synopsys -sv_lib keycontrol_C_code_wrapper

      

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