Why reset handler is located at 0x0 for Cortex-A but not Cortex-M3
What is the reason why the Cortex-M3 has an initial stack pointer located at 0x0 and reset the handler located at 0x4? What is the design rationale for this?
Why don't the ARM guys leave 0x0 in the reset handler like they do for Cortex-A and then initialize the SP inside the reset handler?
source to share
I think this one falls under "this is not a gang, this is a feature."
The ARM architecture profile M (microcontroller) has a completely different exception model for profiles A and R. The A profile (like the R profile) remains backward compatible with previous ARM processors. The M profile was allowed to deviate from this and was therefore designed to be easier to program entirely from C / C ++ (no asm).
This way, vector records contain addresses, not instructions, and once you've done that, why not install SP in the same way? It also performs automatic saving of state when exceptions are recorded.
source to share
all unixsmurf said ...
The traditional approach to the hand was a little odd, the typical approach is a list of addresses rather than a table of instructions. So this could be a factor. But they created an intermittent gobzillion, not just one (a 128/256 deep vector table is not just a handful) and no doubt you don't want to wrap every interrupt before calling C so that the vector table, change / missing modes and stored registers for you, combine this package. You can put the address of the C handler right into the table, including the reset vector, to get the reset vector where you need to have a minimal set of stack pointers before calling, so you need room for the user to specify the initial value of the stack pointer.
source to share