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System-verilog units

I have a wire vector with 64 bits,

wire [63:0] sout;

I want to calculate the sum of these bits, or equivalently, count the number of ones.

What's the best way to do this? (it must be synthesized)

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2 answers


I prefer to use for-loops as they scale more easily and require less typing (and thus less prone to typos).

SystemVerilog (IEEE Std 1800):

logic [$clog2($bits(sout)+1)-1:0] count_ones;

always_comb begin
  count_ones = '0;  
  foreach(sout[idx]) begin
    count_ones += sout[idx];
  end
end


Verilog (IEEE Std 1364-2005):

parameter WIDTH = 64;
// NOTE: $clog2 was added in 1364-2005, not supported in 1364-1995 or 1364-2001
reg [$clog2(WIDTH+1)-1:0] count_ones; 
integer idx;

always @* begin
  count_ones = {WIDTH{1'b0}};  
  for( idx = 0; idx<WIDTH; idx = idx + 1) begin
    count_ones = count_ones + sout[idx];
  end
end
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The "best" is rather subjective, but the simple and clear wording would be:

wire [6:0] sout_sum = sout[63] + sout[62] + ... + sout[1] + sout[0];


You might be able to think a lot and come up with something that gives the best synthesized results, but that's probably a good start until the sync tool says it's not good enough.

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