Assigning values in Verilog: the difference between assignment, <= and =

Question

Assigning values in Verilog: the difference between assignment, <= and =

I've just started learning Verilog and I've seen these three lines from various sources. I am confused about the difference between the three:

c <= a & b;
assign c = ~ a;
c = 1'b0;

These lines seem to be assigning the value to c, but what's the difference? Thank.

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verilog assign

dringx Dec 12. 14 at 2:03

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1 answer

chris · Accepted Answer · 2014-12-12T02:12:17+0000

1) is <=

non-blocking and executed on every positive edge of the clock. they are priced in parallel, so no ordering guarantees. An example of this would be a register.

2) assign =

permanent assignment for out-of-operator posting always. the LHS value is updated when the RHS changes.

3) =

lock assignment, inside always statements provide a consistent order.

Assigning values ​​in Verilog: the difference between assignment, <= and =

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Assigning values in Verilog: the difference between assignment, <= and =