Concatenate arrays of bytes into one array
Is it possible to combine these byte banks:
logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
Something like:
logic [32:0] address_array [0:255];
assign address_array = {bank3, bank2, bank1, bank0}; //!This is pseudocode!
The resulting array is 256 x 32 bits.
Example:
If I want to read addresses 0x0,0x1,0x2,0x3, then I will get address_array [0]. The array index must be between 0 and 255 and 32 bits wide.
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There is no need to use a generator to be used for the loop:
reg [7:0] bank3[0 : 255];
reg [7:0] bank2[0 : 255];
reg [7:0] bank1[0 : 255];
reg [7:0] bank0[0 : 255];
reg [31:0] address_array[0:255];
integer i;
always @* begin
for (i=0;i<256;i=i+1) begin
address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
end
In SystemVerilog:
logic [7:0] bank3[0 : 255];
logic [7:0] bank2[0 : 255];
logic [7:0] bank1[0 : 255];
logic [7:0] bank0[0 : 255];
logic [31:0] address_array[0:255];
always_comb begin
for (int i=0;i<256;i++) begin
address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
end
As Greg mentions, this can also use foreach
:
always_comb begin
foreach ( bank_all[i] ) begin
bank_all[i]= { bank_stack3[i], bank_stack2[i], bank_stack1[i], bank_stack0[i]};
end
end
Solution 2
The question was actually pointing out that instead of having all the banks "stacked" vertically next to each other, so that bank0 is resized to use 32 bits wide. bank0 will be fully read before reaching bank1.
localparam DEPTH = 8;
logic [7:0] bank0[0 : DEPTH-1];
logic [7:0] bank1[0 : DEPTH-1];
logic [7:0] bank2[0 : DEPTH-1];
logic [7:0] bank3[0 : DEPTH-1];
logic [7:0] bank_stack [(DEPTH*4) -1];
logic [(8*4)-1:0] bank_all [0 : DEPTH-1];
always_comb begin
//First reshape vertically stack banks
// IEEE 1800-2012 Section 11.4.14 Streaming operators
{>>{bank_stack}} = {>>{bank0, bank1, bank2, bank3}};
//Second reshape, flatten to 4 bytes wide.
foreach ( bank_all[i] ) begin
bank_all[i]= { bank_stack[i], bank_stack[i+1], bank_stack[i+2], bank_stack[i+3]};
end
end
A short example at the EDA playground .
Thanks to Greg for understanding IEEE 1800-2012 Section 11.4.14 Streaming Operators.
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You can use a generator in a for loop:
reg [7:0] bank3[0 : 255];
reg [7:0] bank2[0 : 255];
reg [7:0] bank1[0 : 255];
reg [7:0] bank0[0 : 255];
wire [31:0] address_array[0:255];
genvar i;
generate
for (i=0;i<256;i=i+1) begin
assign address_array[i] = {bank3[i],bank2[i],bank1[i],bank0[i]};
end
endgenerate
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