How to implement inout parameters?
I know what inout parameters are and how to use them. Suppose we have an inout parameter io
and want to create bi-directional static RAM like the following code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sram IS
port(
clk : IN std_logic;
wr : IN std_logic;
io : INOUT std_logic;
addr : IN INTEGER RANGE 0 TO 7
);
END sram;
ARCHITECTURE behavioral OF sram IS
TYPE matrix IS ARRAY (0 TO 7) OF std_logic;
SIGNAL mem : matrix;
BEGIN
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF wr = '1' THEN
mem(addr) <= io;
END IF;
END IF;
END PROCESS;
io <= mem(addr) WHEN wr = '0' ELSE 'Z';
END behavioral;
We can create an instance of sram and write on it, for example, the following code:
io <= '1' WHEN wr = '1' ELSE 'Z';
Q: How can a synthesis tool manage multiple assignments and judge multiple drivers? What equipment is implemented for this?
Thanks for the comments and responses ...
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For typical FPGAs and ASICs, tristate capabilities are only available in IO, for example, in Altera Arria 10 FPGA:
So, for such devices, internal RAM is always implemented with dedicated input and output ports, so no internal tristate capabilities are used.
Even if the RAM is connected to external IOs that support tristate, then the internal RAM block is still usually created with dedicated input and output ports, so the connection to the tristate-capable pin on the device is handled through an input-enabled buffer and tristate output.
If the internal design tries to use tristate capabilities or multiple drivers if it is not supported by the device, then a synthesis tool will be generated and an error will be generated, usually saying that multiple drivers are not supported for the same network.
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On Xilinx devices, the circuits are similar.
This is a primitive IOBUF image:
The green part is the tristate driven output driver; the blue part is the input driver. A complete IOB (I / O block) consists of several primitives:
- IOB registers (input, output, tristat control)
- delay circuits
- to combine two IOBs into a differential IOB (** BUFDS)
- the ability to generate clock networks (CC-IOB - IOB with clock support)
- pullup, dropldown, ...
- driver (IOBUF)
- pin / ball (IPAD, OPAD, IOPAD) - this includes ESD protection
How does synthesis work?
- Xilinx Synthesis Tools (XST / Synth) add IPAD or OPAD primitives for each wire in the port definition of the top-level component. A pad is simply a primitive to represent the physical pin or ball underneath the FPGA package.
- If you have auto-add I / O buffers enabled, the tool will add IBUF, OBUF, IOBUF, IBUFDS, ... primitives between each PAD and top-level port. It uses the port direction (in, out, inout) to output the correct buffer type. If this option is disabled (default = on), you must manually add buffers for each I / O pin. In some cases XST gets offended: I added some IOBUFs with tristate control manually, so XST refused to dump the missing buffers. So I had to add all the buffers manually ...
When using Xilinx XST, you can use tristate buses (port direction = inout) below the top layer. XST will report that it has added (virtual) tristate buffers. These buffers are truncated if the direction of each bus bit is in an obvious direction and has no problem with multiple drivers.
This does not work in iSim.
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