Piping diagram, Can the ID start if the previous EX uses the same register?

"Usage" is too general, you need to split between reads and writes to the register. If you ask about "reading at the same time" - absolutely that the whole point of pipelining. As long as the register value does not change, there is no problem reading it over and over again. In fact, the ID and EX stages do not use the same resource, so there is no conflict - the value that the EX stage reads comes from the latches that the ID script wrote in the previous loop.

The register you think is the only global value actually has multiple copies along the pipe, each corresponding to its value at some point in the program. If you take the last 2 commands, for example, both read $ r0 and the ID step will read it from the register file for an OR loop on loop 7, write it to the latch, and then read it again in loop 8 for an XOR, while how OR is in the EX stage and at the same time takes a fixed value from the previous loop.

Now the real problem comes when you have a data hazard such as the one caused by the first statement. Since the register value at any given stage must reflect the true value it has according to the program order, you have a problem if you try to execute the EX stage for a Sub instruction in loop 2, because the value of $ r0 was read in the previous loop without representation result of Add. In fact, the value will not be ready in the register file until after Add completes writeback in loop 4. This is called a RAW (read-after-write) conflict and must be fixed or the program will have bogus results. One way to solve this problem is to add a rack when you detect this hazard (as shown in the asterisk diagram) - when the instructions reading $ r0finally continue, they will have the updated value (post Add) already written to the latches. Another (more useful) solution is to add custom logic to bypass the new value when it's ready for all the pipettes it needs. It may still require a break in this case, since the instructions are reversed, so you won't even have time to complete the operation before it needs the next instruction.so you won't even have time to complete the operation before it needs the next instruction.so you won't even have time to complete the operation before it needs the next instruction.

One final note - keep in mind that processors, even as simple as pipelined manipulators, are designed for you. They make you believe that you are running a program you wrote, when in fact they do all kinds of things within themselves without telling you (a slightly more advanced example of this is out-of-order execution). In this case, they make you think the instructions are serialized, when in fact they speculatively run each one before the previous one has finished (or even executed). This of course works most of the time and makes the processor perform much better in terms of instruction throughput (or IPC), but in some cases (data hazards like this, hazard management, etc.) it can completely break your program, so they have to hide it,doing things like adding stalls or flushing a pipe.