Can a dependency be added to another Makefile?
I am not asking if the Makefile can be called from another Makefile .
Suppose I have a rule to create an executable that looks like this:
my-prog: some.o local.o dependencies.o
Please note that I am using inline rules here.
Now, suppose I am starting to use a third party library. I would like to keep this inline syntax and just add the outer rule to the dependency list:
my-prog: some.o local.o dependencies.o somelib/libsomelib.a
But this won't work:
No rule to make target 'somelib/libsomelib.a', needed by 'my-prog'.
I know that I can fix this problem by explicitly calling a different Makefile:
my-prog: some.o local.o dependencies.o
$(MAKE) -C somelib/ libsomelib.a
$(CC) $(LDFLAGS) -o $@ $^ somelib/libsomelib.a
But this is what I am trying to avoid. Any ideas?
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In some cases, it might just be a include
different Makefile, but in those cases they could probably have been written as one in the first place, so ... otherwise, the best thing you can do to make dependency tracking work is extending the recursive make approach - your own makefile can't keep track of dependencies somelib/libsomelib.a
, so you'll have to ask a different Makefile to do it for you each time. I’m afraid it’s not.
However, you can afford to continue using implicit rules and move the tracking of foreign libraries' dependencies to a different makefile. I'm thinking about the lines of fake targets for these other people's compilations:
somelib/libsomelib.a:
$(MAKE) -C somelib/ libsomelib.a
# This target needs to be phony so it is run every time because only the other
# makefile can determine that there nothing to be done.
.PHONY: somelib/libsomelib.a
# then you can use it as a dependency just like locally built targets
my-prog: some.o local.o dependencies.o somelib/libsomelib.a
This can be expanded to include multiple external targets such as:
# list foreign targets here
FOREIGN_TARGETS = \
somelib/libsomelib.a \
foo/libfoo.a \
bar/libbar.a
$(FOREIGN_TARGETS):
# split the target into directory and file path. This assumes that all
# targets directory/filename are built with $(MAKE) -C directory filename
$(MAKE) -C $(dir $@) $(notdir $@)
.PHONY: $(FOREIGN_TARGETS)
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