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The relationship between the CPSID instruction and the general interrupt controller on ARM

I am currently trying to understand the relationship between various ways to mask / disable interrupts in ARM architecture using GIC or cps

.

So far I have collected the following:

  • cps

    can be used to enable / disable interrupts for the processor. Using cpsid i

    disables all interrupts for the processor that issued the instruction (by setting a register cpsr

    ) and cpsie i

    enables interrupts with. This does not change the state of the interrupt distributor or CPU interfaces.
  • Specific interrupts can be masked by writing 1

    to the appropriate bit in one of the registers GICD_ICENABLERn

    in the interrupt distributor.
  • Specific interrupts can also be disabled without setting any targets in the interrupt distributor.

To what extent is this understanding still known?

Now I don't understand how these methods relate to each other. I am assuming the following:

If interrupts are disabled using a register cpsr

and then any interrupt signal is signaled (regardless of whether a level or edge is fired) then the cpu interface will be notified of the interrupt (assuming it is set as target) which changes the state of the interrupt to pending

. Then, as soon as the instruction is issued cpsie i

, the processor switches to interrupt handling.

However, if an interrupt is disabled globally without setting any targets, and an edge-triggered interrupt is signaled, the CPU interface will not change its state. Therefore, if the targets are changed later, the interrupt will not be signaled to any CPU interface (since the trigger is no longer active). This would mean that in this case, interrupts caused by the edge are lost. For interrupts with a level trigger, they will only be sent to the CPU interfaces if the interrupt line is still acknowledged. It's right? Or does the Distributor "remember" the state and if an interrupt was reported, so that in both cases the interrupt will be propagated later?

Now if the interrupt is masked, it will not propagate to any CPU interface again. In this case, however, I expect the interruption to be propagated later after exposure.

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2 answers


To what extent is this understanding still known?

This is mostly correct. The GIC is a separate block for multiprocessor projects. The instructions cpsiX

are in the ARM core. The GIC is further divided into a global distributor (also known as a distribution ) as well as registers for each processor. So in quad-core systems, you will have four GICs for each processor, but only one distributor . Register registers are usually mapped to one address for each core. Of course every core will have a core (and will apply to it cpsiX

).

You can also mask interrupts with registers on each processor like GICC_PMR

etc. and possibly with a peripheral register directly (i.e., the Ethernet controller has an interrupt enable that signals GIC dist → GIC per-CPU → ARM core). The latter will not apply if it is an external interrupt. Often many of the SPI GICs are actually on-chip / SOC-connected, so you can turn off the source.



This would mean that in this case, interrupts caused by the edge are lost. For interrupts with a level trigger, they will only be sent to the CPU interfaces if the interrupt line is still acknowledged. Is it correct?

It seems right. However, I would look at the specifics of our GIC implementation. Typically, this is gic pl390 or gic pl400. Depending on the version of the GIC and the registers available, handling masking, waiting, and canceling can be quite complex. For example, if the CPU can be signaled, but before it handles the interrupt, another CPU has already read and serviced the interrupt. If you only redirect interrupts to one CPU, this does not happen. Then there are interrupt priorities and interrupt interrupts. See Chapter 3.2.1 Disable Priority and Disable Interrupt ARM Generic Interrupt Controller - Architecture Specification .

For edge-triggered interrupts, you need to look before re-enabling interrupts (at distributor level) if the hardware needs to be serviced. The allocator will hold a pending state and if either permission cpsie

is used or enabled for each processor.

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To expand on the “single block” aspect mentioned in the other answer , the ARM processor core has one active low nIRQ line (and the corresponding nFIQ line). The CPSR bits only control how this core reacts to that signal internally - no matter what claimed it was just sitting on the other end, waiting for some sort of response and not knowing what the core was doing.



Likewise, on the other hand, while the CPU GIC interface is designed with a low interrupt priority output and a high interrupt priority output that matches the ARM nIRQ and nFIQ core, there is no reason it couldn't be wired before anything else. (the spec even explains this). Thus, the GIC architecture has no idea what the receiver of these signals is doing with them - cps

it does not matter at all if there is some custom DSP on the other end, and not the core of the ARM architecture.

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