SystemVerilog port type [net or variable]?
I need to clarify SystemVerilog IEEE Std 1800-2012 Ports Section 23.2.2.3.
LRM says that when port type (network type or variable) is omitted on input
-port, it defaults to net type, but when the port input
has data type bit
without specifying the port type, does it output the network type according to LRM?
The answer will be much appreciated!
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The default port type is network and you are referencing it, but 6.7.1. Pure declarations with built-in net types say net types are limited to 4-state integral types. Therefore, you should get an error if you try to declare input bit
instead input var bit
.
Note that earlier versions of SystemVerilog LRM had a default port type of variable when specifying a data type without a port type. Some tools may not generate an error if they are not updated.
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"bit" indicates only the type of data, not the type of network, signal.
When you declare a port as the "foo input bit", the tools are expected to infer the network type based on any default_nettype parameter.
Several verilog style guides have recommended "default_nettype none" as a running tool for spotting typos in network names. This breaks down under the system key as it starts to require everything to be declared with both net and datatype, e.g .:
input wire bit foo
Everyone hates it, so instead:
- do not use "default_nettype none"
- use a real linting tool to do the listing instead.
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