Clever Geek Handbook

Reset VCD (VHDL simulation with vcs)

I need help modeling VHDL code using VCS. What options are available to dump a VcD file from VCS to VHDL code. I have tried all the options I found on the internet. None of them seem to work, or I am not doing it right. A detailed answer would be helpful Teams so far:

    vcs test_top -R +vcs+vcdpluson -debug_pp
    vcs test_top -R +vcs+vcdpluson -debug_pp -vcd test.vcd
    vcs test_top -R +vcs+vcdpluson+vcd_file test.vcd -debug_pp
    vcs test_top -V -R +vcs+vcdpluson -debug_pp
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I think you need to run the simv command as described in this on page 3.



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