Pipeline organization in MIPS
I'm not sure how the following properties affect piping performance for a 5-stage MIPS design (IF, ID, EX, MEM, WB). I just need to be clear.
- only 1 memory port
- no data.
- Branches are closed before the end * of the stage
Does 1 memory port mean that we cannot fetch or write when we read / write to mem (i.e. MEM stage on lw, sw you cannot type IF or other MEM)? Without forwarding, this means that the instruction will not enter the ID stage until after or in the WB stage for the previous instruction it does not depend? Idk, which stands for branch stand
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The general assumption is that you can write in the first half of the loop and read in the second half of the loop.
Let's say that I1 is your first instruction and I2 is the second instruction, and I2 uses the register which is I1 .
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Only 1 memory port . This means that you cannot read or write memory at the same time in two different pipeline stages. For example, if I1 is in the MEM stage , another instruction cannot be in the IF stage at the same because both require memory access.
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No data transfer. The data transfer reflects the fact that at the end of the EX stage for I1, you are transferring data to the I2 ID loop . Therefore, no forwarding means that the pipeline must wait for WB stage I1 to go to stage I2 ID . Assuming you can go to the ID stage at the same time as the WB stage of the previous instruction, because WB will be written to memory during the first half of the cycle, and ID will be read from memory during the second half of the cycle.
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Branches close before the end of the EX stage. This is a common assumption and does not use branch prediction techniques . It simply states that the instruction after the branch must wait for the end of the EX to begin the ID phase . Recall that the address of the next command to be executed is known only at the EX stage of the branch instruction.
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