The fpscr register is not updated when floating point exceptions are enabled in arm7, SIGFPE is not generated
the fpscr register is not updated and no SIGFPE is generated. This has been tested on an NVidia Shield tablet and 1st gen Nexus 7.
feenableexcept(FE_DIVBYZERO | FE_INVALID | FE_OVERFLOW);
The implementation calls the code that ultimately performs this assembly:
asm _volatile__("vmsr fpscr,%0" : :"ri" (fpscr));
; disassembly follows
ldr r3, [r11, #-8]
vmsr fpscr, r3
vmsr fpscr
is not updated. It remains 0x20000010 when it needs to be updated to 0x20000710.
Tested with -mfloat-abi=soft
and -mfloat-abi=softfp
.
What can I conclude?
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ARM ARM has this to say about all the exception / exception bits in FPSCR:
[...]. This bit is RW only if the implementation supports catching floating point exceptions. In an implementation that does not support catching floating point exceptions, this bit is RES0.
The Tegra K1 SoC in SHIELD Tablet has Cortex-A15 processors that do not support VFP exception capture .
The Tegra 3 SoC in the original Nexus 7 has Cortex-A9 processors (with VFP + NEON implementation) that do not support VFP Exception Trap
What's especially gimmicky is that from user space you can't even access the MVFR0 function register to find it programmatically.
I think you can conclude that you don't have hardware that supports excluded traps;)
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