How do I initialize std_logic_vector in VHDL?
I have a signal std_logic_vector (4096 downto 0) and I want to initialize it like below:
architecture Behavioral of test is
type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
signal ram : ram_type;
ram(0) := "0010000000000100";
ram(1) := "0001000000000101";
ram(2) := "0011000000000110";
ram(3) := "0111000000000001";
ram(4) := "0000000000001100";
ram(5) := "0000000000000011";
ram(6) := "0000000000000000";
ram(4095 downto 7) := (others => (others => '0'));
begin
"some code"
end behavioral
for some reason I need to initialize it with these values (I cannot assign these values to them, it must be initialized) is there any way to do this? I tried the above code and it didn't work.
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1 answer
ram
can be initialized like this:
architecture Behavioral of test is
type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
signal ram : ram_type := (0 => "0010000000000100",
1 => "0001000000000101",
2 => "0011000000000110",
3 => "0111000000000001",
4 => "0000000000001100",
5 => "0000000000000011",
6 => "0000000000000000",
others => (others => '0'));
begin
-- Concurrent code
end Behavioral;
But you can look at the specific functions of the FPGA and the tool to see if there is some specific way for the initialization values to be given by the RAM, so the synthesis tool can display it correctly.
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