VHDL BCD loudspeaker code - ERROR: HDLCompiler: 69 - <unsigned> not declared
I am using a tutorial called Digital Systems Design using VHDL (2nd Edition) by Charles R. Roth and Lizzie Curian John. I have been following the VHDL code examples contained in the book, but I have tried a segment that produces errors.
Sample VHDL code is shown below (it comes from the tutorial).
library ieee;
use IEEE.NUMERIC_STD.ALL;
entity BCD_Adder is
Port (
X : in unsigned(7 downto 0);
Y : in unsigned(7 downto 0);
Z : out unsigned(11 downto 0)
);
end BCD_Adder;
architecture BCDadd of BCD_add is
alias Xdig1 : unsigned(3 downto 0) is X(7 downto 4);
alias Xdig0 : unsigned(3 downto 0) is X(3 downto 0);
alias Ydig1 : unsigned(3 downto 0) is Y(7 downto 4);
alias Ydig0 : unsigned(3 downto 0) is Y(3 downto 0);
alias Zdig2 : unsigned(3 downto 0) is Z(11 downto 8);
alias Zdig1 : unsigned(3 downto 0) is Z(7 downto 4);
alias Zdig0 : unsigned(3 downto 0) is Z(3 downto 0);
signal S0 : unsigned(4 downto 0);
signal S1 : unsigned(4 downto 0);
signal C : bit;
begin
S0 <= '0' & Xdig0 + Ydig0; --overloaded +
Zdig0 <= S0(3 downto 0) + 6 when (S0 > 9) else S0(3 downto 0); --add 6 if needed
C <= '1' when (S0 > 9) else '0';
S1 <= '0' & Xdig1 + Ydig1 + unsigned'(0=>C); --type conversion done on C before adding
Zdig1 <= S1(3 downto 0) + 6 when (S1 > 9) else S1(3 downto 0);
Zdig2 <= "0001" when (S1 > 9) else "0000";
end BCDadd;
I am using Xilinx's ISE Project Navigator to simulate VHDL code. When I run the syntax check of the VHDL code it throws the following error: -
ERROR: HDLCompiler: 374 - Line 14: Entity has not been compiled yet. ERROR: HDLCompiler: 69 - Line 16: Not declared. ERROR: HDLCompiler: 69 - Line 17: Not declared. ERROR: HDLCompiler: 69 - Line 19: Not declared. ERROR: HDLCompiler: 69 - Line 20: Not declared. ERROR: HDLCompiler: 69 - Line 22: Not declared. ERROR: HDLCompiler: 69 - Line 23: Not declared. ERROR: HDLCompiler: 69 - Line 24: Not declared. ERROR: HDLCompiler: 69 - Line 26: Not declared. ERROR: HDLCompiler: 69 - Line 27: Not declared.
The error applies to lines starting with an alias . I googled around to see if I can find a solution to this error, but I had no luck. Some websites have mentioned that alias is not supported by most synthesis tools.
Can anyone point me in the right direction to solve this problem.
Many thanks,
Lincoln
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The name of the main module in the architecture declaration does not match the simple name of the object:
entity bcd_adder is
against:
architecture bcdadd of bcd_add is
Convert this to:
architecture bcdadd of bcd_adder is
You must also add
use ieee.std_logic_1164.all;
to your contextual proposal to make std_ulogic visible to implicit conversions from character literals.
Also change the type c
so you don't need another type conversion:
signal c : std_ulogic;
You will find in the appointment
S1 <= '0' & Xdig1 + Ydig1 + unsigned'(0=>C); --type conversion done on C before adding
type C
(bit) is not the underlying unsigned element type (std_ulogic) defined by the qualified expression. In -2008, the numeric_std "+" package also supports an operand that is an unsigned element without using an aggregate to provide an array type.
Then you code, analyze, and without writing a test bench, design and model (which tells us that there are no internal connection problems with ranges).
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