VHDL Assert - Actions Other than Report
I was trying to add an error counter to a VHDL assert operation in existing code. Basically, I have code that looks like this:
assert data = good_data
report "Bad data"
severity error;
And I would like to add something like this to get triggered when this assertion occurs:
errors <= errors + 1;
Now I know I can achieve this by changing the statement to an if statement and then entering the report statement and error count into the counter with an if statement. But I'm wondering if there is anyway to get more functionality out of the already stated statement?
source to share
You can use the VUnit VHDL testing framework https://github.com/LarsAsplund/vunit which has check
both check_equal
wrapping asserts and error counting routines. The default behavior is to stop the first error so that it can be debugged easily.
I also believe OSVVM AlertLogPkg.vhd
has a similar feature. VUnit comes with OSVVM redistributed so you can use it from there.
If you want to roll your own, just create procedure assert(cond : value; msg : string := "")
one that increments the total counter variable in the same package.
source to share
In addition to the parallel assertion statement, there is a sequential assertion statement that can go in the process. Make sure whatever you are testing is in the sensitivity list or wait task with a sensitivity condition. You can execute any number of other sequential statements (e.g. if statements, sequential signal assignment instructions ...).
By definition, statements claim to be passive — they do not change the values of any model objects.
source to share