With the MESI protocol, hitting a record also throws up the processor, right?
I am doing a project that needs to implement a dual processor system with some cache coherency (for which I chose MESI) in VHDL. I just want to confirm this: writing on a separate cache line should cause the cache controller to send invalidation messages on the shared bus, and depending on contention, it should pause the processor for some time, right?
I thought about this scenario; Let's say the processor is doing something like this:
for (int i = 0; i < 5; ++i)
arr[i * 10] = 0; //just so each write is in a different cache line
If the array is entirely in the cache and is shared by other processors, each entry generates an invalid message, each of which performs multiple cycles; in order for the processor to continue executing, all these invalidation messages must be buffered and the buffer will not be limited, so a write hit will have to stop the processor for a while. Am I right about this?
EDIT: Take care to explain the downvote? What part of this question is not clear? Or, if you think this is an idiotic and scary question, I guess you must have an answer for this?
source to share
Don't confuse latency with bandwidth. The invalidation messages will go through several cycles, but you can pipe the process. You can create a pipeline cache that can start processing new invalidation messages before the previous ones have completed.
The MESI protocol does not require all previous messages on different cache lines to be completed before a new message begins.
The in-flight invalidation count will be tied as long as the cache has sufficient bandwidth. If you can generate 1 invalidation message per cycle, and it takes 10 cycles for each message, but your cache can also handle 1 invalidation message per cycle, then up to 10 invalid messages will be sent in flight and your processor should not stall on recording by hitting a common line.
source to share