How to split L2 cache between cores on ARM Cortex-A7?
Context and purpose
I would like to run two completely standalone applications on my Olimex A20 Lime platform that run ARM Cortex-A7. The goal is to allocate one core for each application. So far, so good.
Now I would like to share the L2 cache between cores like this:
L2 cache (256KB)
---------------------------
| CPU0 | CPU1 |
| (128KB) | (128KB) |
---------------------------
Therefore, each core will only have access to its private 128KB L2 cache.
Question
How to split L2 cache between cores on ARM Cortex-A7?
From my point of view, the previous SoC often used an external cache controller like the PL310. Now new SoCs like Cortex-A15 and Cortex-A7 use an onboard cache controller. This controller is somehow integrated into the SCU component.
I found on the CP15 system some cache related registers like CSSELR, CCSIDR, CLIDR, etc., even in the system control register (SCTLR). But none of them allow me to tweak the size for each core. Is it possible to do this?
Thank you for your help.
Edit
Here in a standalone application, I really mean Linux OS . Thus, the goal is to allocate one core for one OS. Therefore, each OS runs (see) a monoprocessor system under it. The entire infrastructure is already working, how good it is.
From the answers I received, I now understand that it should be good for the kernel that both kernels are using L2, even if they are standalone OSs not using the same virtual mapping. In fact, this is really the same as for 2 processes that have a virtual address space.
However, the last thing that worries me is the security aspect:
If both cores share the entire L2 cache, is it technically possible for one core to access the cached data of the other core?
Links
- ARM Cortex-A7 MPCore TRM
- About L2 memory system (7.1)
- Identification registers (4.2.18)
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Two pieces of code that do not use the same physical memory will not cause conflicts in the cache, since the cache is physically tagged on A7 processors (any ARM processor with virtualization extensions).
In A7, cache lines are also tagged with VM tags. Therefore, if you want to ensure separation between the codes running on two cores, you can set up a second pagetable stage for each core and tag them with different VM IDs. Any violation of the address space by EL0 / 1 will trigger a trap for EL2 (Hypervisor). This is very similar to how EL1 provides separation of EL0 address spaces.
To set this up, you will have to have access to the boot code. Usually, from a secure EL1 / EL3 boot code, it directly switches to non-Secure EL1 mode. You will have to change this stream and switch to EL2 mode. In EL2 mode, configure and enable a non-overlapping stage 2 page table for each core. Also tweak the EL2 vector table to catch the 2nd stage MMU exceptions.
This will result in a slight decrease in performance. It will be more efficient than using KVM (last time I checked, KVM is not very good for ARM v7 and causes a lot of design overhead). XEN is more for ARM, but you need a lot of customization on your part.
Unless you plan on using virtualization / stage 2 page tables / SMP extensions; you can also turn off the ACTLR.SMP bit. This may slightly improve performance as the L1 concurrency cache blocks will be disabled.
Note: This answer is for an edited question
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In addition to cache, L2 cache also helps with cache coherency between L1 caches of different cores. If you manage to do this (private L2 caches for each core) you will lose your SMP characteristics. In addition, the L2 cache controller will already take care of loading the cache with data / code used by all cores, which is better than statically splitting caches at boot.
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