STM32 I-CODE and D-CODE buses
The STM32 documentation says the I-CODE and D-CODE buses are connected to the internal flash memory. The I-CODE bus is used to retrieve instructions and the D-CODE bus is used to access data in the code memory area (literal load).
The question is, why are two separate tires used? Can they provide concurrent and completely independent access to flash memory?
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As you can see from the stm32 Reference Manual RM0090 (page 73), the I-CODE and D-CODE buses cannot access the flash independently of the memory, however, they independently access the flash interface:
As for two reasons: they have separate chats, also the I-CODE bus implements prefetching, which is useless for fetching data. Relevant part of the reference manual (page 84):
Data management
Literal pools are fetched from Flash via the D-code bus during the execution phase of the CPU pipeline. Thus, the CPU pipeline stalls until the requested literal pool is provided. To limit the time wasted due to literal pools, AHB data bus D-code access takes precedence over AHB instruction bus I-code access. If some literal pools are frequently used, the data cache can be activated by setting the data cache (DCEN) in the FLASH_ACR register. This function works like an instruction cache, but the size of the saved data is limited to 8 lines of 128 bits.
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