X86_64 - assembly - Why is the offset not 64 bits?
I am reading Intel x86_64 vol.1 manual to find out how memory addressing works.
Nevertheless,
3.7.5 Determination of offset
The offset of a portion of a memory address can be specified directly as a static value (called a move) or by calculating an address made up of one or more of the following:
• Offset - 8-, 16-, or 32-bit value.
I read in Agner Fog's manual that 64-bit absolute addressing is possible when used with the (r / e) ax register.
So..
Is it possible or not to use absolute addressing with 64-bit addresses in jmp, mov and call (with all registers), or I will have to keep using Base + offset
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Please note that it mov absolute_addr64, %rax
is only available with rax
as a target. mov $imm64, %reg
available for any register.
See Loading from a 64-bit address into a different register than rax .
When AMD designed the AMD64 architecture, they basically said that 2GB of code should be enough for everyone.
http://www.x86-64.org/documentation/abi.pdf describes small, medium and large code models.
-
small: Normal 32-bit relative movements for each offset, call, and memory. (All characters are known to be between
0
and2^31 - 2^24 - 1
). -
medium: small code, but the data section is divided into two parts: regular and large (
.ldata
,lrodata
,.lbss
).This model requires the compiler to use instructions
movabs
for accessing large static data and for loading addresses into registers, but retains the advantages of a small code model for manipulating addresses in small sections of data and text (branch-specific)By default, only data larger than 65535 bytes will be placed in a large data section
-
large:
The compiler must use the statement
movabs
as in the middle code model, even to process addresses within the text section. In addition, when branching, indirect branches are required to addresses whose offset from the current instruction pointer is unknown.It is possible to eliminate the limitation of the text section in the small and medium models by splitting the program into several shared libraries, so this model is strictly required if the text of one function becomes larger than the text of the medium model allows.
The PIC average should < movabs / lea / add
generate RIP-relative addresses with more than 32-bit offsets.
Large PICs need to be able to address the global offset table and the procedure link table too.
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I don't think x86 architectures have 64 bit offsets or offsets.
The reason is simple: the "ease" of programming they provide doesn't come up often enough to matter. Statistically, most of the offsets you need are pretty small. When you need a 64-bit offset (very rare), you can always simulate with the ADD instruction with little or no performance penalty. Transistors to do 64 bit bias are best spent doing something else.
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