How do I initialize the vectors register?

Question

I have defined the case of vectors like this

val my_reg = Reg(Vec(n, Bits(32.W)))

and I access the elements of this register in a for loop using my_reg(i)

.

Now I like to initialize this register to zero, so I change the definition of the variable to this

val my_reg = Reg(Vec(n, Bits(32.W)), init = UInt(0))

However, I am getting the following compilation error when I want to access the elements of this register

chisel3.core.Data does not take parameters
my_reg(i) := io.a(i)

How can I detect the case of the vectors and initialize them correctly synchronously?

+3

Mahdi Apr 26. 17 at 23:10

1 answer

Chick markley · Accepted Answer · 2017-04-27T16:23:39+0000

Use RegInit instead. I believe the following expression will do what you want

    val my_reg = RegInit(Vec(Seq.fill(n)(0.U(32.W))))

The vector is initialized by Seq from UInt to zeros that are 32 bits wide.