LOCK CMPXCHG on non-cached memory?

The content of this answer is very similar to the content of this article by Dr. Dobbs , in particular the "Blocking" section, which I consulted to understand blocking on systems with QuickPath Interconnect (QPI) support.
Thus, this post has been tagged as a "community wiki".

Yes it is possible.

The 8086 did not have a cache, but it was able to perform atomic operations .
This was achieved by introducing the #lock signal in the FSB . When this signal was asserted, no new transaction could be started by any agent - only a lock could be performed (in fact, even a lock sometimes ) - thereby quiescing on the system.

With the introduction of caching, the need for bus blocking has been reduced. The processor can manage its cache by delaying any snooping request from other agents for the duration of the block.
However, the legacy bus lock was retained due to backward compatibility and because the guarded variable spanned two cache lines .

When the FSB was dropped in favor of QPI (consider dropping the hub architecture and multiprocessor systems), the #lock signal was also disabled.

Now one of the QPI agents is created as Quiesce Master (QM). When the processor wants a lock, it requests QM, which in turn informs other agents, including DMA agents, to terminate any future request.
When each agent has confirmed QM, it informs the initiator of the lock that the system is locked. An atomic operation is then performed, and upon completion, the requested unlock is requested. Finally, QM will continue to inform other agents that new transactions are allowed again.
Thus, mechanisms for locking the entire memory subsystem are still present and functioning in modern projects.