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Initializing data in Mem (Chisel)

I would like to initialize the memory bitmem

by setting all bits to 1 on first initialization. I've seen inits

used for ROM and I'm wondering if there are similar ways to initialize a value in Mem

?

val bitmem = Mem(Bits(width = conf.ways), (conf.cache_lines*conf.words_per_line)
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Drilling equipment is primarily designed for ASIC design. So the focus is on the synthesized hardware, so that when you simulate the bit code, you are simulating the same thing that you are synthesizing. Since it is Mem

designed to be mapped to SRAM in the ASIC and SRAM cannot be initialized, we do not support this design in the bit itself. If you want to create registers instead of SRAM, try Reg of Vec .

However, the ability to initialize Mems is clearly a useful feature for modeling. We are in the process of updating Chisel Testers and this feature is for first class. We also discuss that the Chisel API can help users initialize their memories in Verilog or SystemVerilog testbenches .



At the same time, as a workaround, you can parameterize your design based on whether memory (or memory) should be initialized (i.e. if you are developing for simulation or synthesis) and emit Reg of Vec when you simulate and Mem. if you haven't.

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