What is the PCIE equivalent of "Cache Line Size"?

In the PCI configuration space, the cache line size indicates the size of the system cache in DWORD units. This register must be implemented by master devices that can generate the Write Write and Invalidate command.

The value in this register is also used by the master devices to determine whether read, line read, or multi-command read should be used to access memory.

Slave devices that want to resolve memory gaps using cache line bind mode must implement this register in order to know when a sequence of packets is wrapped at the beginning of a cache line.

However, this field is implemented by PCI Express devices as a read / write field for legacy compatibility purposes, but does not affect the behavior of the PCI Express device.

Then, how does the PCIe system implement the memory-write-invalidate function?