Getting all the declared signals of an object

I want to have an elegant way to add a logic analyzer to an entity (chipcope for xilinx fpgas). As described in ug936 , it is possible to add an attribute to a signal (see page 10). This tells Vivado to store the signal names (more or less) so that I can add them to the logic analyzer core. The described method has the disadvantage that I have to do it manually for each signal that I want to track. This makes this method very error prone.

Is there any possibility in vhdl to get all the declared signals inside the object and loop over it and assign the attribute in a loop?