How do I know if a register is a "general register"?

The term "general purpose register" (GPR) stands in contrast to a special purpose register. The latter cannot be used in all contexts.

Historically, the old 8086 architecture introduced this distinction for the integer registers present in their names until today:

• AX = A register ccumulator: accumulates result (**)
• BX = B register ase: base offset for a specific instruction, eg. XLAT
• CX = C register ounter: counting for loops, eg. JCXZ .
• DX = D ata register: expands the data range, eg. the MUL result is in DX: AX
• SI = S is our index: source for string instructions eg. LODSB
• DI = D indexing index: assignment for string instructions, eg. STOSB
• SP = S Bind Pointer: points to the current stack item
• BP = B pointer ase: points to the base of the current subroutine (stack frame)

(**) AX / AL is a kind of special register. Many instructions have special encodings for AX / AL as operands, for example. load segment registers from MOV .

Other special purpose registers were

• Segment registers (CS, DS, ES, SS)
• Flags register (FLAGS) and
• Instruction Pointer (IP)

Some of these restrictions are still in use today in addressing mode for 16-bit instructions in real mode (see Intel® 64 and IA-32 Architectures Software Developers Guide Volume 2, Section 2.1.5, Table 2-1. "16 -bit addressing forms with ModR / M byte ")

With the introduction of the 32-bit architecture - IA-32 - the purpose of generic and integer registers of each register can be used for all purposes (hence general purpose). This is also reflected in the coding of the instruction addressing mode, see Intel Manual Volume 2, Section 2.1.5, Table 2.2. (Compare Table 2.1 with Table 2.2 to get an idea of ​​the difference)

The names were prefixed with E and R in EAX and RAX, respectively, and their historical names indicating use are now just conditional.

With many new architectures, new special target registers have been added. For a complete overview, see Intel Handbook Volume 1, Section 3.7.2 .:

• 32-bit general purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)
• 16-bit general purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP)
• 8-bit general purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL)
• segment registers (CS, DS, SS, ES, FS and GS)
• EFLAGS register
• x87 FPU Registers (ST0 - ST7, Status Word, Control Word, Tag Word, Data Operand Pointer and Pointer Instruction)
• MMX registers (MM0 to MM7)
• XMM Registers (XMM0 to XMM7) and MXCSR Register
• control registers (CR0, CR2, CR3, and CR4) and system table pointer registers (GDTR, LDTR, IDTR and task register)
• debug registers (DR0, DR1, DR2, DR3, DR6 and DR7)
• MSR registers

A general register is one that can be used for multiple purposes. These goals are

• value
• decision
• indexing
• (count)
• (base)

The segment register, for example, can only hold the segment value, but cannot be used in an appendix. And FPU register can only contain floating point value, but cannot be used for addressing.

In IA-32, the ESP register is closer to a general-purpose register because it can be used for (almost) all of the above purposes:

• as meaning: mov eax, esp
  
  
• in the address: mov eax, [esp+4]
  
  but not as a (scaled) index likemov eax, [4+esp*2]
  
  
• as a base: mov eax, [esp + eax]
  
  
• as count: inc esp
  
  before the jump is done

The only exception to this ESP

is that (scaled) indexed addressing cannot be encoded. It can only be used as a base register, which is exclusively encoded with the SIB byte (see Intel Manual, Volume 2, Section 2.1.5, Table 2.3 - see Footer).

To illustrate the coding difference between ESP and other registers (like ECX):

8b 01         mov eax, [ecx]   ; MOV + ModRM (normal)
8b 04 24      mov eax, [esp]   ; MOV + ModRM + SIB byte
8b 41 04      mov eax, [ecx+4] ; MOV + ModRM + disp8
8b 44 24 04   mov eax, [esp+4] ; MOV + ModRM + SIB + disp8

      

        
        
        
      

    

I think, despite this one exception ESP

, it can still be considered a GPR.