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Software creation tool

I need something like make ie dependencies + execute shell commands when failing command stops executing. But more deeply integrated with the shell, that is, now each line is executed in a separate context, so it's not easy to set a variable to one line and use it on the next line (I don't want the escape char at the end of the line, because that is not readable). I want a simple syntax (no XML) with control flow and functions (which is missing in make). It doesn't need support to compile. I should just bundle a few autotools built components, package them, run the test and publish the results.

I looked at: make, ant, maven, scons, waf, nant, rake, cons, cmake, jam and they don't match my needs.

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Given that you want control flow, functions, all working in the same environment and without XML, it looks like you want to use the available shell script (sh / bash / ksh / zsh) or Perl (insert your favorite scripting language here!).



Note that you haven't watched aap . I'm not familiar with this, other than that it makes the system from the people who brought us vim. Therefore, you can view this.

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take a look at doit



  • you can use shell commands or python functions to define tasks (assemblies).
  • very easy to use. write scripts in python. "no api" (you don't need to import anything in your script)
  • it has good support for tracking dependencies and goals.
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Have a look at fabricate .

If that doesn't suit your needs, or if you don't want to write your build script in Python, you can also use a combination of shell and fabrication scripts. Write the script as you would for building your project manually, but add build calls with "fabricate.py" so that build dependencies are automatically managed.

Simple example:

#!/bin/bash
EXE="myapp"
CC="fabricate.py gcc" # let fabricate handle dependencies
FILES="file1.c file2.c file3.c"
OBJS=""

# build link
for F in $FILES; do
    echo $CC -c $F
    if [ $? -ne 0 ]; then
        echo "Build failed while compiling $F" >2
        exit $?
    fi
    OBJS="$OBJS ${F/.c/.o}"
done

# link
$CC -o $EXE $OBJS
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Mixing a makefile and a scripting language to choose which makefile to run at the same time can do this.

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I had the same needs. My current solution is to use makefiles to represent graph dependencies accurately (you should read "Recursive Considered Harmful" ). These makefiles run bash scripts that take makefile options as parameters. This way you don't have to deal with the shell context issue and get a clear separation between dependencies and actions.

I am currently reviewing waf as it looks well designed and fast enough.

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You might want to look at SCons ; it is a Make-replacement written in Python.

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