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Make: a hierarchical make file

(disclaimer: I'm used to Brazilians ... I'm somewhat inexperienced in making)

Context: I am using Eclipse CDT which generates makefiles.

Let's say I have a project directory 'lib' and 2 build configurations 'Debug' and 'Release'. Eclipse CDT gracefully creates a makefile for each build configuration. The mentioned makefile is in the Debug and Vacation folders.

Now I want to make a makefile in the lib folder that calls the makefiles 'Debug / makefile' and 'Release / makefile'.

How to do it?

I want to run "make" in the "lib" folder and both config will be called with the specified targets.

Solution Based on all the big inputs collected here, I worked out the following:

MAKE=make
BUILDS=Release Debug
TARGETS=all clean

$(TARGETS):
    @for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done

$(BUILDS):
    @for t in $(TARGETS) ; do $(MAKE) -C $@ $$t ; done

%:
    @for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done
+2


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4 answers


depends on what the "calls" are. Do you want either

include $(BUILD)/Makefile

or

$(MAKE) -C $(BUILD) $@

or some of them. I think you need the last one. Maybe something like



release debug:
    $(MAKE) -C $@

You get the idea.

Other examples:

BUILDS=release debug
TARGETS=all clean

$(TARGETS):
    for b in $(BUILDS) ; do $(MAKE) -C $$b $@ ; done

$(BUILDS):
    for t in $(TARGETS) ; do $(MAKE) -C $@ $$t ; done
+3


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Since you are mentioning "specified target (s)", I suggest:

%:
    $ (MAKE) -C Debug $ @ 
    $ (MAKE) -C Release $ @


If this is too general, you can replace% with $ (TARGETS), where TARGETS is what you define, a list of all the things you would ever want to do.

+2


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all: release debug

release:
   $(MAKE) -C ../Release

debug:
   $(MAKE) -C ../Debug

I guess they are all on the same level. The path must be from where you call Make.

+1


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Have different targets that call makefile in two directories.

all: debug product

debug:
        $(MAKE) -f debug/Makefile

product:
        $(MAKE) -f product/Makefile
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