TAP (Test Anything Protocol) for Verilog or SystemVerilog
Is there a TAP ( Test Anything Protocol ) for Verilog? It would be nice, because then I could use validation to check my results automatically.
Update: 10/9/09: asked why not use assertions. Partially TAP gives me good reporting like file count and test count. It can also be used with a glow device to report progress over time.
12/10/09: I am looking for a minimal implementation with a number of tests at the beginning and at the end, and in ok, diag and fail modes. is () would be nice, but not necessary.
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I don't think there is a built-in TAP implementation for Verilog. I would say the whole point of using TAP is that adding a TAP generator is relatively easy. If you plan on doing a lot of work at Verilog, you can write your own.
However, have you looked at veripool ? You can use Verilog :: Parser as a bridge to generate TAP output, which you could use with TAP :: Parser and Test :: Harness .
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