Does the cache line support TLB access?
Assuming we deliberately beat the DTLB and would like to continue clearing a single cache line from L1-3 using clflush
an area of memory that (most likely) does not overlap with the addresses pointed to by the TLB entry; does this actually lead to the base page address of the cache line, which we throw in the TLB again?
In short, will a clflush
affect TLB at all? My guess is that thanks to this consistency instruction, it will subsequently write that string back to memory (obviously a TLB lookup is required.)
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In the Intel® 64 and IA-32 Architect Software Design Guide, Volume 2A: Instruction Set Reference, AL: "Invalidation of the cache line that contains the linear address specified by the source operand from all levels of the processor cache hierarchy (data and instructions).
Since it uses a linear (virtual) address, the address must be translated, which means that traversing the page table would be required to skip the TLB. (This usually applies even to different types of instructions that push cache entries to higher cache levels, since L1 caches are usually physically labeled for x86. In general, tagging with a virtual address is out of fashion. A physical address for tags means the physical address is needed to check the cache for a hit, so even if it wasn't sent to memory, a translation would be required.)
While it might be possible to avoid loading the TLB for such accesses, the added complexity of such special case handling would almost certainly not be considered as valuable if CLFLUSH were not commonly used.
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