What's the best way to write the registration path in Verilog
solution 1
reg q;
always @(posedge clk or negedge rst_n)
if (!rst_n)
q <= 1'b0;
else
if (en_a)
q <= da;
else if (en_b)
q <= db;
else if (en_c)
q <= dc;
solution2
reg qw, qr;
always @(*)
if (en_a)
qw = da;
else if (en_b)
qw = db;
else if (en_c)
qw = dc;
always @(posedge clk or negedge rst_n)
if (!rst_n)
qr <= 1'b0;
else
qr <= qw;
I use a solution 1
lot and I can find it a lot in the code of many other engineers. Solution 2
separates the combinational logic part and the sequential logic part, classic FSM style.
My question is (for Solution 2
) is there an actual advantage over solution 1
? And what is the difference between the two solutions?
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This depends in part on the size of the design and synthesizer. For large FSM constructs, the two block-based approaches use less area, often have better times and fewer lines of code, then its equivalent is always blocked. This article from Cliff Cummings details the differences between one, two, three always block approaches. For a while, he recommended this style in some old documents here and here . A few years ago, my team compared styles to our own code and tools; we can come to the same conclusion as Cliff. You should try to compare yourself.
There are always two advantages of a block:
- See the next flop value in front of the clock in the waveform or display instructions. With one always block, you need to compute values.
- Don't accidentally create an unintended trigger
- Note: There is a risk of an unintentional latch being pulled out, however, since there are several intended latches in the design, they are easy to spot in the line and synthesis tool reports. An unintentional flip flop is harder to spot.
- All combinational logic is grouped.
- Simple ECO Guide. Usually fewer lines of code to change.
- No need to worry about accidental mixing and non-blocking.
- For large structures:
- Several lines of code
- Smaller area
- Best time
The advantages of each block are as follows:
- Generally, one always block is slightly more simulation efficient than two always blocks - ( Cliff SNUG1998SJ FSM , p. 10)
- Don't accidentally pull out an unintentional latch
- When IEEE1364-1995 is strictly followed:
-
@(*)
was added in IEEE1364-2001. In IEEE1364-1995, every external external signal used in a combination always block must be listed in the foreign list.- Example:
@(en_a or en_b or en_c or da or db or dc or qr)
- Example:
-
- For small structures:
- Only one block to view
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